- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄300082 > V54C3128164VB6 (MOSEL-VITELIC) 8M X 16 SYNCHRONOUS DRAM, 5.4 ns, PBGA60 PDF資料下載
參數(shù)資料
| 型號： | V54C3128164VB6 |
| 廠商： | MOSEL-VITELIC |
| 元件分類： | DRAM |
| 英文描述： | 8M X 16 SYNCHRONOUS DRAM, 5.4 ns, PBGA60 |
| 封裝： | WBGA-60 |
| 文件頁數(shù)： | 1/45頁 |
| 文件大?。?/td> | 871K |
| 代理商： | V54C3128164VB6 |
當(dāng)前第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁
MOSEL VITELIC
1
V54C3128(16/80/40)4V(BGA)
128Mbit SDRAM
3.3 VOLT, BGA PACKAGE
8M X 16
16M X 8
32M X 4
V54C3128(16/80/40)4V(BGA) Rev. 1.2 September 2001
PRELIMINARY
67PC
78PC
System Frequency (fCK)
166 MHz
143 MHz
125 MHz
Clock Cycle Time (tCK3)
6 ns
7 ns
8 ns
Clock Access Time (tAC3)CAS Latency = 3
5.4 ns
6 ns
Clock Access Time (tAC2) CAS Latency = 2
5.4 ns
6 ns
Features
s 4 banksx2Mbit x16 organization
s 4 banks x 4Mbit x 8 organization
s 4 banks x 8Mbit x 4 organization
s High speed data transfer rates up to 166 MHz
s Full Synchronous Dynamic RAM, with all signals
referenced to clock rising edge
s Single Pulsed RAS Interface
s Data Mask for Read/Write Control
s Four Banks controlled by BA0 & BA1
s Programmable CAS Latency: 2, 3
s Programmable Wrap Sequence: Sequential or
Interleave
s Programmable Burst Length:
1, 2, 4, 8 for Sequential Type
1, 2, 4, 8 for Interleave Type
s Multiple Burst Read with Single Write Operation
s Automatic and Controlled Precharge Command
s Random Column Address every CLK (1-N Rule)
s Power Down Mode
s Auto Refresh and Self Refresh
s Refresh Interval: 4096 cycles/64 ms
s Availablein60Pin WBGA
s LVTTL Interface
s Single +3.3 V
±0.3 V Power Supply
Description
The V54C3128(16/80/40)4V(BGA) is a four bank
Synchronous DRAM organized as 4 banks x 2Mbit
x 16, 4 banks x 4Mbit x 8, or 4 banks x 8Mbit x 4.
The V54C3128(16/80/40)4V(BGA) achieves high
speed data transfer rates up to 166 MHz by employ-
ing a chip architecture that prefetches multiple bits
and then synchronizes the output data to a system
clock
All of the control, address, data input and output
circuits are synchronized with the positive edge of
an externally supplied clock.
Operating the four memory banks in an inter-
leaved fashion allows random access operation to
occur at higher rate than is possible with standard
DRAMs. A sequential and gapless data rate of up to
166 MHz is possible depending on burst length,
CAS latency and speed grade of the device.
Device Usage Chart
Operating
Temperature
Range
Package Outline
Access Time (ns)
Power
Temperature
Mark
B6
7PC
7
8PC
Std.
L
0
°Cto 70°C
Blank
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| V54C3256404VDLJ8PC | 64M X 4 SYNCHRONOUS DRAM, 6 ns, PBGA60 |
| V54C328404VCT8 | x4 SDRAM |
| V54C328804VCT7 | x8 SDRAM |
| V54C328804VCT8 | x8 SDRAM |
| V54C365164VEF6 | 4M X 16 SYNCHRONOUS DRAM, 5.4 ns, PBGA60 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| V54C3128164VBGA | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:128Mbit SDRAM 3.3 VOLT, BGA PACKAGE |
| V54C3128164VBI7 | 制造商:PROMOS 功能描述: 制造商:ProMOS Technologies Inc 功能描述:8M X 16 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
| V54C3128164VS | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:128Mbit SDRAM 3.3 VOLT, TSOP II / SOC PACKAGE 8M X 16, 16M X 8, 32M X 4 |
| V54C3128164VT | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:128Mbit SDRAM 3.3 VOLT, TSOP II / SOC PACKAGE 8M X 16, 16M X 8, 32M X 4 |
| V54C3128404VBGA | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:128Mbit SDRAM 3.3 VOLT, BGA PACKAGE |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。