- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄359325 > V53C8258H (Mosel Vitelic, Corp.) HIGH PERFORMANCE 256K X 8 EDO PAGE MODE CMOS DYNAMIC RAM PDF資料下載
參數(shù)資料
| 型號(hào)： | V53C8258H |
| 廠商： | Mosel Vitelic, Corp. |
| 英文描述： | HIGH PERFORMANCE 256K X 8 EDO PAGE MODE CMOS DYNAMIC RAM |
| 中文描述： | 高性能256K × 8 EDO公司頁面模式的CMOS動(dòng)態(tài)隨機(jī)存儲(chǔ)器 |
| 文件頁數(shù)： | 16/18頁 |
| 文件大小： | 219K |
| 代理商： | V53C8258H |
16
MOSEL VITELIC
V53C8258H
V53C8258H Rev. 1.4 February 1997
Data Output Operation
The V53C8258H Input/Output is controlled by
OE
,
CAS
,
WE
and
RAS
. A
RAS
low transition
enables the transfer of data to and from the
selected row address in the Memory Array. A
RAS
high transition disables data transfer and latches
the output data if the output is enabled. After a
memory cycle is initiated with a
RAS
low transition,
a
CAS
low transition or
CAS
low level enables the
internal I/O path. A
CAS
high transition or a
CAS
high level disables the I/O path and the output driver
if it is enabled. A
CAS
low transition while
RAS
is
high has no effect on the I/O data path or on the
output drivers. The output drivers, when otherwise
enabled, can be disabled by holding
OE
high. The
OE
signal has no effect on any data stored in the
output latches. A
WE
low level can also disable the
output drivers when
CAS
is low. During a Write
cycle, if
WE
goes low at a time in relationship to
CAS
that would normally cause the outputs to be
active, it is necessary to use
OE
to disable the
output drivers prior to the
WE
low transition to allow
Data In Setup Time (t
DS
) to be satisfied.
Power-On
After application of the V
CC
supply, an initial
pause of 200
μ
s is required followed by a minimum
of 8 initialization cycles (any combination of cycles
containing a
RAS
clock). Eight initialization cycles
are required after extended periods of bias without
clocks (greater than the Refresh Interval).
During Power-On, the V
CC
current requirement of
the V53C8258H is dependent on the input levels of
RAS
and
CAS
. If
RAS
is low during Power-On, the
device will go into an active cycle and I
CC
will exhibit
current transients. It is recommended that
RAS
and
CAS
track with V
CC
or be held at a valid V
IH
during
Power-On to avoid current surges.
Table 1. V53C8258H Data Output
Operation for Various Cycle Types
Cycle Type
I/O State
Read Cycles
Data from Addressed
Memory Cell
CAS
-Controlled Write
Cycle (Early Write)
High-Z
WE
-Controlled Write
Cycle (Late Write)
OE
Controlled. High
OE
= High-Z I/Os
Read-Modify-Write
Cycles
Data from Addressed
Memory Cell
EDO Read Cycle
Data from Addressed
Memory Cell
EDO Write Cycle
(Early Write)
High-Z
EDO Read-Modify-
Write Cycle
Data from Addressed
Memory Cell
RAS
-only Refresh
High-Z
CAS
-before-
RAS
Refresh Cycle
Data remains as in
previous cycle
CAS
-only Cycles
High-Z
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| V53C8258H35 | HIGH PERFORMANCE 256K X 8 EDO PAGE MODE CMOS DYNAMIC RAM |
| V53C8258H40 | HIGH PERFORMANCE 256K X 8 EDO PAGE MODE CMOS DYNAMIC RAM |
| V53C8258H45 | HIGH PERFORMANCE 256K X 8 EDO PAGE MODE CMOS DYNAMIC RAM |
| V53C8258H50 | HIGH PERFORMANCE 256K X 8 EDO PAGE MODE CMOS DYNAMIC RAM |
| V53C8258L | Ultra-High Speed,3.3 Volt 256K x 8 Bit EDO Page Mode CMOS Dynamic RAM(3.3V超高速256Kx8EDO頁面模式CMOS動(dòng)態(tài)RAM) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| V53C864K10L | 制造商:VITELIC 功能描述: |
| V53C864K80L | 制造商:VITELIC 功能描述: |
| V5-4/RK 4-0.3/0.3/0.3 | 制造商:TURCK Inc 功能描述:Cordset, Splitter, M12 Female Straight x 3, 4 Wire, 4m, PVC, Yellow |
| V-5410EK | 制造商:Honeywell Sensing and Control 功能描述:V Basics |
| V541S001-6ZZ00-000 | 制造商:Carling Technologies 功能描述:V-SERIES ROCKER SWITCH - Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。