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參數(shù)資料
| 型號： | V53C8258H |
| 廠商： | Mosel Vitelic, Corp. |
| 英文描述： | HIGH PERFORMANCE 256K X 8 EDO PAGE MODE CMOS DYNAMIC RAM |
| 中文描述： | 高性能256K × 8 EDO公司頁面模式的CMOS動態(tài)隨機存儲器 |
| 文件頁數(shù)： | 15/18頁 |
| 文件大?。?/td> | 219K |
| 代理商： | V53C8258H |
15
MOSEL VITELIC
V53C8258H
V53C8258H Rev. 1.4 February 1997
Functional Description
The V53C8258H is a CMOS dynamic RAM
optimized for high data bandwidth, low power
applications. It is functionally similar to a traditional
dynamic RAM. The V53C8258H reads and writes
data by multiplexing an 18-bit address into a 9-bit
row and a 9-bit column address. The row address is
latched by the Row Address Strobe (
RAS
). The
column address “flows through” an internal address
buffer and is latched by the Column Address Strobe
(
CAS
). Because access time is primarily dependent
on a valid column address rather than the precise
time that the
CAS
edge occurs, the delay time from
RAS
to
CAS
has little effect on the access time.
Memory Cycle
A memory cycle is initiated by bringing
RAS
low.
Any memory cycle, once initiated, must not be
ended or aborted before the minimum t
RAS
time has
expired. This ensures proper device operation and
data integrity. A new cycle must not be initiated until
the minimum precharge time t
RP
/t
CP
has elapsed.
Read Cycle
A Read cycle is performed by holding the Write
Enable (
WE
) signal High during a
RAS
/
CAS
operation. The column address must be held for a
minimum specified by t
AR
. Data Out becomes valid
only when t
OAC
, t
RAC
, t
CAA
and t
CAC
are all satisifed.
As a result, the access time is dependent on the
timing relationships between these parameters. For
example, the access time is limited by t
CAA
when
t
RAC
, t
CAC
and t
OAC
are all satisfied.
Write Cycle
A Write Cycle is performed by taking
WE
and
CAS
low during a
RAS
operation. The column
address is latched by
CAS
. The Write Cycle can be
WE
controlled or
CAS
controlled depending on
whether
WE
or
CAS
falls later. Consequently, the
input data must be valid at or before the falling edge
of
WE
or
CAS
, whichever occurs last. In the
CAS
-
controlled Write Cycle, when the leading edge of
WE
occurs prior to the
CAS
low transition, the I/O
data pins will be in the High-Z state at the beginning
of the Write function. Ending the Write with
RAS
or
CAS
will maintain the output in the High-Z state.
In the
WE
controlled Write Cycle,
OE
must be in
the high state and t
OED
must be satisfied.
Extended Data Output Page Mode
EDO Page operation permits all 512 columns
within a selected row of the device to be randomly
accessed at a high data rate. Maintaining
RAS
low
while performing successive
CAS
cycles retains the
row address internally and eliminates the need to
reapply it for each cycle. The column address buffer
acts as a transparent or flow-through latch while
CAS
is high. Thus, access begins from the
occurrence of a valid column address rather than
from the falling edge of
CAS
, eliminating t
ASC
and t
T
from the critical timing path.
CAS
latches the
address into the column address buffer. During
EDO operation, Read, Write, Read-Modify-Write or
Read-Write-Read cycles are possible at random
addresses within a row. Following the initial entry
cycle into Hyper Page Mode, access is t
CAA
or t
CAP
controlled. If the column address is valid prior to the
rising edge of
CAS
, the access time is referenced to
the
CAS
rising edge and is specified by t
CAP
. If the
column address is valid after the rising
CAS
edge,
access is timed from the occurrence of a valid
address and is specified by t
CAA
. In both cases, the
falling edge of
CAS
latches the address and
enables the output.
EDO provides a sustained data rate of 71 MHz for
applications that require high bandwidth such as
bit-mapped graphics or high-speed signal
processing. The following equation can be used to
calculate the maximum data rate:
512
Data Rate =
t
RC
+ 511 x t
PC
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