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參數資料
| 型號： | V53C8258H50 |
| 廠商： | Mosel Vitelic, Corp. |
| 英文描述： | HIGH PERFORMANCE 256K X 8 EDO PAGE MODE CMOS DYNAMIC RAM |
| 中文描述： | 高性能256K × 8 EDO公司頁面模式的CMOS動態(tài)隨機存儲器 |
| 文件頁數： | 1/18頁 |
| 文件大?。?/td> | 219K |
| 代理商： | V53C8258H50 |
1
MOSEL VITELIC
PV53C8258H
V53C8258H Rev. 1.4 February 1997
HIGH PERFORMANCE
35
40
45
50
Max.
RAS
Access Time, (t
RAC
)
35 ns
40 ns
45 ns
50 ns
Max. Column Address Access Time, (t
CAA
)
18 ns
20 ns
22 ns
24 ns
Min. Extended Data Out Page Mode Cycle Time, (t
PC
)
14 ns
15 ns
17 ns
19 ns
Min. Read/Write Cycle Time, (t
RC
)
70 ns
75 ns
80 ns
90 ns
Features
I
256K x 8-bit organization
I
EDO Page Mode for a sustained data rate
of 71 MHz
I
RAS
access time: 35, 40, 45, 50 ns
I
Low power dissipation
I
Read-Modify-Write,
RAS
-Only Refresh,
CAS
-Before-
RAS
Refresh capability
I
Refresh Interval: 512 cycles/8 ms
I
Available in 24 pin 300 mil Plastic DIP,
26/24 pin 300 mil SOJ and 28-pin 300 mil
TSOP-I packages
I
Single 5V
±
10% Power Supply
I
TTL Interface
Description
The V53C8258H is a high speed 262,144 x 8 bit
CMOS dynamic random access memory.
The V53C8258H offers a combination of features:
Page Mode with Extended Data Output for high
data bandwidth, and Low CMOS standby current.
All inputs and outputs are TTL compatible. Input
and output capacitances are significantly lowered to
allow increased system performance. Page Mode
with Extended Data Output operation allows
random access of up to 512 (x8) bits within a row
with cycle times as fast as 14 ns. Because of static
circuitry, the
CAS
clock is not in the critical timing
path. The flow-through column address latches
allow address pipelining while relaxing many critical
system timing requirements. The V53C8258H is
ideally suited for graphics, digital signal processing
and high-performance computing systems.
V53C8258H
HIGH PERFORMANCE
256K X 8 EDO PAGE MODE
CMOS DYNAMIC RAM
Device Usage Chart
Operating
Temperature
Range
Package Outline
Access Time (ns)
Power
Temperature
Mark
P
K
T
35
40
45
50
Std.
0
°
C to 70
°
C
Blank
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