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參數(shù)資料
| 型號(hào)： | V53C8125HT50 |
| 廠商： | MOSEL-VITELIC |
| 元件分類： | DRAM |
| 英文描述： | 128K X 8 FAST PAGE DRAM, 50 ns, PDSO28 |
| 封裝： | TSOP1-28 |
| 文件頁數(shù)： | 1/17頁 |
| 文件大?。?/td> | 1527K |
| 代理商： | V53C8125HT50 |
MOSEL VITELIC
1
V53C8125H
ULTRA-HIGH PERFORMANCE,
128K X 8 FAST PAGE MODE
CMOS DYNAMIC RAM
PRELIMINARY
HIGH PERFORMANCE
30
35
40
45
50
Max. RAS Access Time, (tRAC)
30 ns
35 ns
40 ns
45 ns
50 ns
Max. Column Address Access Time, (tCAA)
16 ns
18 ns
20 ns
22 ns
24 ns
Min. Fast Page Mode Cycle Time, (tPC)
19 ns
21 ns
23 ns
25 ns
28 ns
Min. Read/Write Cycle Time, (tRC)
65 ns
70 ns
75 ns
80 ns
90 ns
Features
s 128K x 8-bit organization
s RAS access time: 30, 35, 40, 45, 50 ns
s Fast Page Mode supports sustained data rates
up to 53 MHz
s Read-Modify-Write, RAS-Only Refresh,
CAS-Before-RAS Refresh capability
s Refresh Interval: 256 cycles/8 ms
s
TSOP-I packages
Description
The V53C8125H is a high speed 131,072 x 8 bit
CMOS dynamic random access memory. The
V53C8125H offers a combination of features: Fast
Page Mode for high data bandwidth, fast usable
speed, CMOS standby current.
All inputs and outputs are TTL compatible. Input
and output capacitances are significantly lowered to
allow increased system performance. Fast Page
Mode operation allows random access of up to 512
columns (x9) bits within a row with cycle times as
short as 19 ns. Because of static circuitry, the CAS
clock is not in the critical timing path. The flow-
through column address latches allow address
pipelining while relaxing many critical system timing
requirements for fast usable speed. These features
make the V53C8125H ideally suited for graphics,
digital signal processing and high performance pe-
ripherals.
Device Usage Chart
Operating
Temperature
Range
Package Outline
Access Time (ns)
Power
Temperature
Mark
K
T
30
35
40
45
50
Std.
0
°C to 70 °C
.
Blank
V53C8125H Rev. 1.7 August 1998
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