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參數(shù)資料
| 型號(hào)： | V53C8125LK60LE |
| 廠商： | MOSEL-VITELIC |
| 元件分類： | DRAM |
| 英文描述： | 128K X 8 FAST PAGE DRAM, 60 ns, PDSO24 |
| 封裝： | 0.300 INCH, SOJ-26/24 |
| 文件頁(yè)數(shù)： | 1/18頁(yè) |
| 文件大小： | 224K |
| 代理商： | V53C8125LK60LE |
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MOSEL VITELIC
1
V53C8125L
ULTRA-HIGH PERFORMANCE,
3.3 VOLT 128K x 8 BIT FAST PAGE MODE
CMOS DYNAMIC RAM
PRELIMINARY
V53C8125L Rev. 1.4 November 1997
HIGH PERFORMANCE
60
Max. RAS Access Time, (tRAC)
60 ns
Max. Column Address Access Time, (tCAA)
30 ns
Min. Fast Page Mode Cycle Time, (tPC)
40 ns
Min. Read/Write Cycle Time, (tRC)
120 ns
Features
s 128K x 8-bit organization
s Fast Page Mode supports sustained data rates
of 25 MHz
s RAS access time: 60 ns
s Read-Modify-Write, RAS-Only Refresh,
CAS-Before-RAS Refresh capability
s Refresh Interval: 256 cycles/8 ms
s Available in 26/24 pin 300 mil SOJ and
28-pin TSOP-I packages
s Single +3.3 V
± 0.3 V power supply
s TTL Interface
Description
The V53C8125L is a high speed 131,072 x 8 bit
CMOS dynamic random access memory. The
V53C8125L offers a combination of features: Fast
Page Mode for high data bandwidth, fast usable
speed, CMOS standby current.
All inputs and outputs are TTL compatible. Input
and output capacitances are significantly lowered to
allow increased system performance. Fast Page
Mode operation allows random access of up to 512
columns (x9) bits within a row with cycle times as
short as 40 ns. Because of static circuitry, the CAS
clock is not in the critical timing path. The flow-
through column address latches allow address
pipelining while relaxing many critical system timing
requirements for fast usable speed. These features
make the V53C8125L ideally suited for graphics,
digital signal processing and high performance pe-
ripherals.
Device Usage Chart
Operating
Temperature
Range
Package Outline
Access Time (ns)
Power
Temperature
Mark
K
T
60
Std.
0
°C to 70°C
Blank
-40
°C to 85°C
I
-55
°C to 125°C
E
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