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參數(shù)資料
| 型號(hào)： | V53C808H |
| 廠商： | Mosel Vitelic, Corp. |
| 英文描述： | HIGH PERFORMANCE 1M x 8 BIT EDO PAGE MODE CMOS DYNAMIC RAM OPTIONAL SELF REFRESH |
| 中文描述： | 高性能100萬× 8位EDO公司頁面模式的CMOS動(dòng)態(tài)隨機(jī)存儲(chǔ)器可選自刷新 |
| 文件頁數(shù)： | 16/18頁 |
| 文件大小： | 136K |
| 代理商： | V53C808H |
16
V53C808H Rev. 1.5 April 1998
MOSEL V ITELIC
V53C808H
Power-On
After application of the V
CC
supply, an initial
pause of 200
m
s is required followed by a minimum
of 8 initialization cycles (any combination of cycles
containing a RAS clock). Eight initialization cycles
are required after extended periods of bias without
clocks (greater than the Refresh Interval).
During Power-On, the V
CC
current requirement of
the V53C808H is dependent on the input levels of
RAS and CAS. If RAS is low during Power-On, the
device will go into an active cycle and I
CC
will exhibit
current transients. It is recommended that RAS and
CAS track with V
CC
or be held at a valid V
IH
during
Power-On to avoid current surges.
Table 1. V53C808H Data Output
Operation for Various Cycle Types
Cycle Type
I/O State
Read Cycles
Data from Addressed
Memory Cell
CAS-Controlled Write
Cycle (Early Write)
High-Z
WE-Controlled Write
Cycle (Late Write)
OE Controlled.
High OE = High-Z I/Os
Read-Modify-Write
Cycles
Data from Addressed
Memory Cell
EDO Read Cycle
Data from Addressed
Memory Cell
EDO Write Cycle
(Early Write)
High-Z
EDO Read-Modify-
Write Cycle
Data from Addressed
Memory Cell
RAS-only Refresh
High-Z
CAS-before-RAS
Refresh Cycle
Data remains as in
previous cycle
CAS-only Cycles
High-Z
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