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參數(shù)資料
| 型號： | UTI760A |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | UTI760A RTS Remote Terminal for Stores |
| 中文描述： | UTI760A轉(zhuǎn)運站遠程終端為商店 |
| 文件頁數(shù)： | 7/48頁 |
| 文件大?。?/td> | 928K |
| 代理商： | UTI760A |
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RTS-7
Status Register (Read Only):
The 16-bit read-only Status Register provides the RTS system status. Read the Status Register by applying a logic 0 to CTRL,
CS, and OE, and a logic 1 to RD/WR. The 16-bit contents of the Status Register are read from data I/O pins DATA(15:0).
Bit
Number
Initial
Condition
Description
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
[0]
[0]
[0]
[0]
[0]
[0]
MCSA0. The LSB of the mode code or subaddress as indicated by the logic state of bit 5.
MCSA1. Mode code or subaddress as indicated by the logic state of bit 5.
MCSA2. Mode code or subaddress as indicated by the logic state of bit 5.
MCSA3. Mode code or subaddress as indicated by the logic state of bit 5.
MCSA4. Mode code or subaddress as indicated by the logic state of bit 5.
MC/SA. A logic 1 indicates that bits 4 through 0 are the subaddress of the last command word,
and that the last command word was a normal transmit or receive command. A logic 0 indicates
that bits 4 through 0 are a mode code, and that the last command was a mode command.
Channel A/B. A logic 1 indicates that the most recent command arrived on Channel A; a logic 0
indicates that it arrived on Channel B.
Channel B Enabled. A logic 1 indicates that Channel B is available for both reception and
transmission.
Channel A Enabled. A logic 1 indicates that Channel A is available for both reception and
transmission.
Terminal Flag Enabled. A logic 1 indicates that the Bus Controller has not issued an Inhibit
Terminal Flag Mode Code. A logic 0 indicates that the Bus Controller, via the above mode
code, is overriding the host system’s ability to set the Terminal Flag bit of the status word.
Busy. A logic 1 indicates the Busy bit is set. This bit is reset when the System Busy bit in the
Control Register is reset.
Self-Test. A logic 1 indicates that the chip is in the internal self-test mode. This bit is reset
when the self-test is terminated.
TA Parity Error. A logic 1 indicates the wrong Terminal Address parity; it causes the biphase
inputs to be disabled. TA Parity Error results in the Message Error bit being set to a logic one,
and Channels A and B become disabled.
Message Error. A logic 1 indicates that a message error has occurred since the last Status Reg-
ister read. This bit is not reset until the Status Register has been examined. Message error con-
dition must be removed before reading the Status Register to reset the Message Error bit.
Valid Message. A logic 1 indicates that a valid message has been received since the last Status
Register read. This bit is not reset until the Status Register has been examined.
Terminal Active. A logic 1 indicates the device is executing a transmit or receive operation.
Same as TERACT output except active high. (Always TERACT; never DSCNCT.)
[] - Values in parentheses indicate the initialized values of these bits.
Bit 6
[1]
Bit 7
[1]
Bit 8
[1]
Bit 9
[1]
Bit 10
[1]
Bit 11
[0]
Bit 12
[0]
Bit 13
[0]
Bit 14
[0]
Bit 15
[0]
SELF-
TEST
TERM
ACTV
VAL
MESS
MESS
ERR
TAPA
ERR
BUSY TFEN CH A
EN
CH B
EN
CHNL
A/B
MCSA
4
MCSA
3
MCSA
2
MCSA
1
MCSA
0
MC/
SA
[0]
LSB
[0]
[0]
[0]
[0]
[0]
[1]
[1]
[1]
[1]
[1]
[0]
[0]
[0]
[0]
[0]
MSB
[ ] defines reset state
STATUS REGISTER (READ ONLY):
Figure 4b. Status Register
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