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參數(shù)資料
| 型號： | UTI760A |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | UTI760A RTS Remote Terminal for Stores |
| 中文描述： | UTI760A轉(zhuǎn)運(yùn)站遠(yuǎn)程終端為商店 |
| 文件頁數(shù)： | 12/48頁 |
| 文件大?。?/td> | 928K |
| 代理商： | UTI760A |
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RTS-12
1.6 Terminal Address
The Terminal Address of the RTS is programmed via five
input pins: RTA(4:0) and RTPTY. Asserting MRST latches
the RTS’s Terminal Address from pins RTA(4:0) and parity
bit RTPTY. The address and parity cannot change until the
next assertion of the MRST. The parity of the Terminal
Address is odd; input pin RTPTY is set to a logic state to
satisfy this requirement. A logic 1 on Status Register
bit 12 indicates incorrect Terminal Address parity. An
example follows:
RTA(4:0) = 05 (hex) = 00101
RTPTY = 1 (hex) = 1
Sum of 1’s = 3 (odd), Status Register bit 12 = 0
RTA(4:0) = 04 (hex) = 00100
RTPTY = 0 (hex) = 0
Sum of 1’s = 1 (odd), Status Register bit 12 = 0
RTA(4:0) = 04 (hex) = 00100
RTPTY = 1 (hex) = 1
Sum of 1’s = 2 (even), Status Register bit 12 = 1
The RTS checks the Terminal Address and parity on Master
Reset. The state of the DSCNCT signal indicates the mated
status of the store. When all six Terminal Address pins
(RTA(4:0), RTPTY) go to a logic one, the DSCNCT pin is
asserted. To enable the disconnect function (DSCNCT pin)
bit 11 of the Control Register is set to a logic one. With
broadcast disabled, RTA (4:0) = 11111 operates as a normal
RT address.
1.7 Internal Self-Test
Setting bit 6 of the Control Register to a logic one enables
the internal self-test. Disable Channels A and B at this time
to prevent bus activity during self-test by setting bits 0 and
1 of the Control Register to a logic zero. Normal operation
is inhibited when internal self-test is enabled. The self-test
capability of the RTS is based on the fact that the MIL-STD-
1553B status word sync pulse is identical to the command
word sync pulse. Thus, if the status word from the encoder
is fed back to the decoder, the RTS will recognize the
incoming status word as a command word and thus cause
the RTS to transmit another status word. After the host
invokes self-test, the RTS self-test logic forces a status word
transmission even though the RTS has not received a valid
command. The status word is sent to decoder A or B
depending on the channel the host selected for self-test. The
self-test is controlled by the host periodically changing the
bit patterns in the status word being transmitted. Writing to
the Control Register bits 2, 3, 4, 7, 8, and 10 changes the
status word. Monitor the self-test by sampling either the
Status Register or the external status pins (i.e., Command
Strobe (COMSTR), Transmit/Receive (T/R)). For more
detailed explanation of internal self-test, consult UTMC
publication
RTR/RTS Internal Self-Test Routine.
1.8 Power-up and Master Reset
After power-up, reset initializes the part with its biphase
ports enabled, latches the Terminal Address, selects Notice
III subaddress decoding, and turns on the busy option. The
device is ready to accept commands from the MIL-STD-
1553B bus. The busy flag is asserted while the host is loading
the message pointers and messages. After this task is
completed, the host removes the busy condition via a
Control Register write to the RTS. On power-up if the
terminal address parity (odd) is incorrect, the biphase inputs
are disabled and the message error pin (MERR) is asserted.
This condition can also be monitored via bit 12 of the Status
Register. The MERR pin is negated on reception of first
valid command.
1.9 Encoder and Decoder
The RTS interfaces directly to a bus transmitter/ receiver via
the RTS Manchester II encoder/decoder. The UT1760A
RTS receives the command word from the MIL-STD-
1553B bus and processes it either by the primary or
secondary decoder. Each decoder checks for the proper sync
pulse and Manchester waveform, edge skew, correct number
of bits, and parity. If the command is a receive command,
the RTS processes each incoming data word for correct
format and checks the control logic for correct word count
and contiguous data. If an invalid message error is detected,
the message error pin is asserted, the RTS ceases processing
the remainder (if any) of the message, and it then suppresses
status word transmission. Upon command validation
recognition, the external status outputs are enabled.
Reception of illegal commands does not suppress status
word transmission.
The RTS automatically compares the transmitted word
(encoder word) to the reflected decoder word by way of the
continuous loop-back feature. If the encoder word and
reflected word do not match, the transmitter error pin
(TXERR) is asserted. In addition to the loop-back compare
test, a timer precludes a transmission greater than 760μs by
the assertion of Fail-safe Timer (TIMERON). This timer is
reset upon receipt of another command. (RT-to-RT transfer
time-out = 57μs).
1.10 RT-RT Transfer Compare
The RT-to-RT Terminal Address compare logic makes sure
that the incoming status word’s Terminal Address matches
the Terminal Address of the transmitting RT specified in the
command word. An incorrect match results in setting the
message error bit and suppressing transmission of the
status word.
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