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參數(shù)資料
| 型號： | UTI760A |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | UTI760A RTS Remote Terminal for Stores |
| 中文描述： | UTI760A轉(zhuǎn)運站遠程終端為商店 |
| 文件頁數(shù)： | 13/48頁 |
| 文件大?。?/td> | 928K |
| 代理商： | UTI760A |
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RTS-13
1.11 Illegal Command Decoding
The host has the option of asserting the ILLCOM pin to
illegalize a received command word. On receipt of an illegal
command, the RTS sets the Message Error bit in the status
word, sets the message error output, and sets the message
error latch in the Status Register.
The following RTS outputs may be used to externally
decode an illegal command, Mode Code or Subaddress
indicator (MC/SA), Mode Code or Subaddress bus
MCSA(4:0), Command Strobe (COMSTR), Broadcast
(BRDCST), and Remote Terminal to Remote Terminal
transfer (RTRT) (see figure 21 on page 34.)
To illegalize a transmit command, the ILLCOM pin must
be asserted within 3.3μs after VALMSG goes to a logic 1 if
the RTS is to respond with the Message Error bit of the status
word at a logic 1. If the illegal command is mode code 2, 4,
5, 6, 7, or 18, the ILLCOM pin must be asserted within 664ns
after Command Strobe (COMSTR) transitions to logic 0.
Asserting the ILLCOM pin within the 664ns inhibits the
mode code function. For mode code illegalization, assert the
ILLCOM pin until the VALMSG signal is asserted.
For an illegal receive command, the ILLCOM pin must be
asserted within 18.2μs after the COMSTR transitions to a
logic 0 in order to suppress data words from being stored.
In addition, the ILLCOM pin must be at a logic 1 throughout
the reception of the message until VALMSG is asserted.
This does not apply to illegal transmit commands since the
status word is transmitted first.
The above timing conditions also apply when the host
externally decodes an illegal broadcast command. The host
must remove the illegal command condition so that the next
command is not falsely decoded as illegal.
2.0 M
EMORY
M
AP
E
XAMPLE
Figures 5 and 6 illustrate the UT1760A RTS buffering three
receive command messages to Subaddress 4. The receive
message pointer for Subaddress 4 is located at 03C4 (hex)
in the 1K x 16 RAM. The 16-bit contents of location 03C4
(hex) point to the memory location where the first receive
message is stored. The Address Field defined as bits 0
through 9 of address 03C4 (hex) contain address
information. The Index Field defined as bits 10 through 15
of address 03C4 (hex) contain the message buffer index (i.e.,
number of messages buffered).
Figure 5 demonstrates the updating of the message pointer
as each message is received and stored. The memory storage
of these three messages is shown in figure 6. After receiving
the third message for Subaddress 4 (i.e., Index Field equals
zero) the Address Field of the message pointer is not
incremented. If the host does not update the receive
message pointer for Subaddress 4 before the next receive
command for Subaddress 4 is accepted, the third message
will be overwritten.
Figures 7 and 8 show an example of multiple message
retrieval from Subaddress 16 upon reception of a MIL-STD-
1553B transmit command. The message pointer for transmit
Subaddress 16 is located at 03F0 (hex) in the 1K x 16 RAM.
The 16-bit contents of location 03F0 (hex) point to the
memory location where the first message data words
are stored.
Figure 7 demonstrates the updating of the message pointer
as each message is received and stored. The data memory
for these three messages is shown in figure 8.
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