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參數(shù)資料
| 型號： | UTI760A |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | UTI760A RTS Remote Terminal for Stores |
| 中文描述： | UTI760A轉(zhuǎn)運(yùn)站遠(yuǎn)程終端為商店 |
| 文件頁數(shù)： | 6/48頁 |
| 文件大小： | 928K |
| 代理商： | UTI760A |
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RTS-6
Control Register (Write Only)
The 13-bit write-only Control Register manages the operation of the RTS. Write to the Control Register by applying a logic
one to OE, and a logic zero to CTRL, CS, and RD/WR. Data is loaded into the Control Register via I/O pins DATA(12:0).
Control register write must occur 50ns before the rising edge of COMSTR to latch data into the outgoing status word.
Bit
Number
Bit 0
Bit 1
Bit 2
Bit 3
Initial
Condition
[1]
[1]
[0]
[1]
Description
Channel A Enable. A logic 1 enables Channel A biphase inputs.
Channel B Enable. A logic 1 enables Channel B biphase inputs.
Terminal Flag. A logic 1 sets the Terminal Flag bit of the Status Word.
System Busy. A logic 1 sets the Busy bit of the Status Word and limits RTS access to the
memory. No data word can be retrieved or stored; command words will be stored.
Subsystem Busy. A logic 1 sets the Subsystem Flag bit of the Status Word.
Self-Test Channel Select. This bit selects which channel the self-test checks; a logic 1 selects
Channel A and a logic 0 selects Channel B.
Self-Test Enable. A logic 1 places the RTS in the internal self-test mode and inhibits normal
operation. Channels A and B should be disabled if self-test is chosen.
Service Request. A logic 1 sets the Service Request bit of the Status Word.
Instrumentation. A logic 1 sets the Instrumentation bit of the Status Word.
Broadcast Enable. A logic 1 enables the RTS to recognize broadcast commands.
Notice Select. A logic 1 enables Notice III operation; logic 0 enables Notice I or II operation.
DSCNCT/TERACT Pin Select. A logic 1 selects the “Disconnect” function; a logic 0 selects
the “Terminal Active” function.
RBUSY Time Select. A logic 1 selects a 5.7
μ
s RBUSY alert; a logic 0 selects a 2.7
μ
s
RBUSY alert.
[] - Values in parentheses indicate the initialized values of these bits.
Bit 4
Bit 5
[0]
[0]
Bit 6
[0]
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
[0]
[0]
[1]
[1]
[1]
Bit 12
[1]
X
X
X
NO
TICE
PS
BCEN
INS
SRQ
ITST
SUBS BUSY
CH B
EN
CH A
EN
ITCS
RBUSY
TS
[1]
LSB
Figure 4a. Control Register
[1]
[0]
[1]
[0]
[0]
[0]
[0]
[0]
[1]
[1]
[1]
[1]
[ ] defines reset state
CONTROL REGISTER (WRITE ONLY):
MSB
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