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參數(shù)資料
| 型號(hào)： | UT80C196KD-WCC |
| 英文描述： | MICROCONTROLLER|16-BIT|8096 CPU|CMOS|QFL|68PIN|PLASTIC |
| 中文描述： | 單片機(jī)| 16位| 8096的CPU |的CMOS | QFL | 68PIN |塑料 |
| 文件頁(yè)數(shù)： | 4/42頁(yè) |
| 文件大?。?/td> | 190K |
| 代理商： | UT80C196KD-WCC |
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4
Table 6. Interrupt Vector Sources, Locations, and Priorities
Number
Interrupt Vector
Source(s)
Interrupt
Vector
Location
PTS
Vector
Location
Priority
1
(0 is the
Lowest
Priority)
Special
Unimplemented
Opcode
Unimplemented Opcode
2012h
N/A
N/A
Special
Software Trap
Software Trap
2010h
N/A
N/A
INT 15
NMI
2
NMI
203Eh
N/A
15
INT 14
HSI FIFO Full
HSI FIFO Full
203Ch
205Ch
14
INT 13
EXTINT 1
2
Port 2.2
203Ah
205Ah
13
INT 12
Timer 2 Overflow
Timer 2 Overflow
2038h
2058h
12
INT 11
Timer 2 Capture
2
Timer 2 Capture
2036h
2056h
11
INT 10
HSI FIFO 4
HSI FIFO
Fourth Entry
2034h
2054h
10
INT 9
Receive
RI Flag
3
2032h
2052h
9
INT 8
Transmit
TI Flag
3
2030h
2050h
8
INT 7
EXTINT
2
Port 2.2 or Port 0.7
200Eh
204Eh
7
INT 6
Serial Port
RI Flag and
TI Flag
4
200Ch
204Ch
6
INT 5
Software Timer
Software Timer 0-3
Timer 2 Reset
200Ah
204Ah
5
INT 4
HSI.0
2
HSI.0 Pin
2008h
2048h
4
INT 3
High Speed
Outputs
Events on HSO.0 thru
HSO.5 Lines
2006h
2046h
3
INT 2
HSI Data Available
HSI FIFO Full or
HSI Holding Reg.
Loaded
2004h
2044h
2
INT 1
EDAC Bit Error
Single Bit Error
Single Bit Error OVF
Double Bit Error
2002h
2042h
1
INT 0
Timer Overflow
Timer 1 or Timer 2
2000h
2040h
0
All of the previous maskable interrupts can be assigned to the PTS.
Any PTS interrupt has priority over all other maskable interrupts.
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