參數(shù)資料
型號: UT80C196KD-WCC
英文描述: MICROCONTROLLER|16-BIT|8096 CPU|CMOS|QFL|68PIN|PLASTIC
中文描述: 單片機(jī)| 16位| 8096的CPU |的CMOS | QFL | 68PIN |塑料
文件頁數(shù): 35/42頁
文件大小: 190K
代理商: UT80C196KD-WCC
35
Table 12. Serial Port Timing
SYMBOL
PARAMETER
MINIMUM
MAXIMUM
UNIT
t
XLXL2
Serial port clock period (BRR > 8002H)
6 T
OSC typical
ns
t
XLXH
1
Serial port clock falling edge to rising edge
(BRR > 8002H)
4 T
OSC
-50
4 T
OSC
+50
ns
t
XLXL
2
Serial port clock period (BRR = 8001H)
4 T
OSC
typical
ns
t
XLXH
1
Serial port clock falling edge to rising edge
(BRR = 8001H)
2 T
OSC
-50
2 T
OSC
+50
ns
t
QVXH
1
Output data valid to clock rising edge
2 T
OSC
-50
ns
t
XHQX1
Output data hold after clock rising edge
2 T
OSC
-50
ns
t
XHQV
1
Next output data valid after clock rising edge
2 T
OSC
+50
ns
t
DVXH
1
Input data setup to clock rising edge
T
OSC
+50
ns
t
XHDX1
Input data hold after clock rising edge
0
ns
t
XHQZ
1
Last clock rising to output float
2 T
OSC
-10
2 T
OSC
+10
ns
TXD
RXD (OUT)
RXD (IN)
0
1
2
3
4
5
6
7
T
XLXL
t
QVXH
t
XHQV
t
XHQX
t
DVXH
t
XHDX
t
XLXH
t
XHQZ
Figure 12. Serial Port Waveform - Shift Register Mode
0
1
2
3
5
4
7
6
Note :
1. Tested only at initial qualification, and after my design or process changes which may affect this characteristic.
2. These specs are verified functional vectors (strobed) only.
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