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參數(shù)資料
| 型號(hào)： | UT80C196KD-WCC |
| 英文描述： | MICROCONTROLLER|16-BIT|8096 CPU|CMOS|QFL|68PIN|PLASTIC |
| 中文描述： | 單片機(jī)| 16位| 8096的CPU |的CMOS | QFL | 68PIN |塑料 |
| 文件頁(yè)數(shù)： | 27/42頁(yè) |
| 文件大?。?/td> | 190K |
| 代理商： | UT80C196KD-WCC |
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27
Note:
* Post-radiation performance guaranteed at 25
°
C per MIL-STD-883 Method 1019 at 1.0E5 rads(Si).
1. If max exceeded, additional wait state occurs.
2. If wait states are used, add 2 T
OSC
*N, where N = number of wait states.
3. Assuming back-to-back bus cycles.
4. 8-bit only
5. Tested only at initial qualification, and after any design or process changes which may affect this characteristic.
6. These specs are verified using functional vectors (strobed) only.
7. Low speed tests performed at 5MHz. 1MHz operation is guaranteed by design.
t
LLWL
5
ALE falling edge to WR falling edge
T
OSC
- 10
T
OSC
+10
ns
t
CLWL
CLKOUT low to WR falling edge
-5
+10
ns
t
QVWH2
Data stable to WR rising edge
T
OSC
- 10
T
OSC
+10
ns
t
CHWH
5
CLKOUT high to WR rising edge
-10
+15
ns
t
WLWH
2,5
WR low period
T
OSC
- 10
ns
t
WHQX
5
Data hold after WR rising edge
T
OSC
- 10
T
OSC
+10
ns
t
WHLH
3,5
WR rising edge to ALE rising edge
T
OSC
- 10
T
OSC
+10
ns
t
WHBX5
BHE, INST after WR rising edge
T
OSC
- 10
T
OSC
+10
ns
t
WHAX4,5
AD8-15 HOLD after WR rising
T
OSC
- 25
ns
t
RHBX
5
BHE, INST after RD rising edge
T
OSC
- 10
T
OSC
+10
ns
t
RHAX
4,5
AD8-15 HOLD after RD rising
T
OSC
- 25
ns
t
AVENV
5
Address valid to EDACEN valid
2T
OSC
-30
ns
t
LHENX
5
EDACEN hold after ALE high
0
ns
t
AVEV
2,5
Address valid to EDAC input valid
3T
OSC
-29
ns
t
RXEX5
EDAC hold after RD inactive
0
T
OSC
-10
ns
t
EVWH2,5
EDAC output stable to WR rising
T
OSC
-10
T
OSC
+10
ns
t
WHEX
5
EDAC output hold after WR rising
T
OSC
-10
T
OSC
+10
ns
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