參數(shù)資料
型號: UT80C196KD-WCA
英文描述: MICROCONTROLLER|16-BIT|8096 CPU|CMOS|QFL|68PIN|PLASTIC
中文描述: 單片機| 16位| 8096的CPU |的CMOS | QFL | 68PIN |塑料
文件頁數(shù): 26/42頁
文件大?。?/td> 190K
代理商: UT80C196KD-WCA
5.0 AC CHARACTERISTICS READ CYCLE
(V
DD
= 5.0V
±
10%) (T
C
= -55
°
C to +125
°
C for "C" screening and -40
°
C to +125
°
C for "W" screening)
SYMBOL
PARAMETER
MINIMUM
MAXIMUM
UNIT
t
AVYV5
Address VALID to READY setup
2T
OSC
- 30
ns
t
YLYH
5
Non-READY time
No upper limit
ns
t
CLYX
1,5
READY hold after CLKOUT low
0
2T
OSC
- 20
ns
t
LLYX
1,5
READY hold after ALE low
T
OSC
3T
OSC
- 20
ns
t
AVGV
5
Address valid to BUSWIDTH setup
2T
OSC
- 30
ns
t
CLGX
5
BUSWIDTH hold after CLKOUT low
0
ns
t
AVDV2,5
Address valid to input data valid
3T
OSC
- 29
ns
t
RLDV2
RD Active to input data valid
5 (see Note 5)
T
OSC
- 26
ns
t
CLDV
5
CLKOUT low to input data valid
5
T
OSC
- 26
ns
t
RHDZ
5
End of RD to input data float
0
T
OSC
-10
ns
t
RXDX
5
Data hold after RD inactive
0
T
OSC
-10
ns
f
OSC
5
Frequency on XTAL1
1 (see Note 7)
20 (see Note 6)
Mhz
T
OSC5
XTAL1 period (1/f
OSC
)
50 (see Note 6)
1000 (see Note 7)
ns
t
XHCH
XTAL1 high to CLKOUT high or low
0
+25
ns
t
CLCL
6
CLKOUT cycle time
2T
OSC
Typical
ns
t
CHCL5
CLKOUT high period
T
OSC
- 10
T
OSC
+10
ns
t
CLLH
CLKOUT falling edge to ALE rising
-5
+15
ns
t
LLCH
5
ALE falling edge to CLKOUT rising
-10
+10
ns
t
LHLH2, 6
ALE cycle time
4T
OSC
Typical
ns
t
LHLL5
ALE high period
T
OSC
- 10
T
OSC
+15
ns
t
AVLL5
Address setup to ALE falling edge
T
OSC
- 15
ns
t
LLAX
Address hold after ALE falling edge
T
OSC
- 20
T
OSC
+5
ns
t
LLRL
ALE falling edge to RD falling edge
T
OSC
- 5
T
OSC
+10
ns
t
RLCL
RD low to CLKOUT falling edge
-5
+10
ns
t
RLRH
2
RD low period
T
OSC
- 5
ns
t
RHLH
3,5
RD rising edge to ALE rising edge
T
OSC
-10
T
OSC
+10
ns
t
RLAZ
5
RD low to address float
-5
+5
ns
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