- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄361591 > uPSD3254B-24T1T (意法半導(dǎo)體) Flash Programmable System Devices with 8032 Microcontroller Core PDF資料下載
參數(shù)資料
| 型號： | uPSD3254B-24T1T |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Flash Programmable System Devices with 8032 Microcontroller Core |
| 中文描述： | 閃存可編程系統(tǒng)設(shè)備與8032微控制器內(nèi)核 |
| 文件頁數(shù)： | 64/175頁 |
| 文件大小： | 1731K |
| 代理商： | UPSD3254B-24T1T |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁當(dāng)前第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁
UPSD3254A, UPSD3254BV, UPSD3253B, UPSD3253BV
64/175
The timer can be configured for either “timer” or
“counter” operation. In the most typical applica-
tions, it is configured for “timer” operation (C/T2 =
0). “Timer” operation is a little different for Timer 2
when it’s being used as a baud rate generator.
Normally, as a timer it would increment every ma-
chine cycle (thus at the 1/6 the CPU clock frequen-
cy). In the case, the baud rate is given by the
formula:
Mode 1,3 Baud Rate =
f
OSC
/ (32 x [65536 – (RCAP2H, RCAP2L)]
where (RCAP2H, RCAP2L) is the content of
RC2H and RC2L taken as a 16-bit unsigned inte-
ger.
Timer 2 also be used as the Baud Rate Generating
Mode. This mode is valid only if RCLK + TCLK = 1
in T2CON or in PCON.
Note:
A roll-over in TH2 does not set TF2, and will
not generate an interrupt. Therefore, the Timer In-
terrupt does not have to be disabled when Timer 2
is in the Baud Rate Generator Mode.
Note:
If EXEN2 is set, a 1-to-0 transition in T2EX
will set EXF2 but will not cause a reload from
(RCAP2H, RCAP2L) to (TH2, TL2). Thus when
Timer 2 is in use as a baud rate generator, T2EX
can be used as an extra external interrupt, if de-
sired.
It should be noted that when Timer 2 is running
(TR2 = 1) in “timer” function in the Baud Rate Gen-
erator Mode, one should not try to READ or
WRITE TH2 or TL2. Under these conditions the
timer is being incremented every state time, and
the results of a READ or WRITE may not be accu-
rate. The RC registers may be read, but should not
be written to, because a WRITE might overlap a
reload and cause WRITE and/or reload errors.
Turn the timer off (clear TR2) before accessing the
Timer 2 or RC registers, in this case.
More About Mode 0.
Serial data enters and exits
through RxD. TxD outputs the shift clock. 8 bits are
transmitted/received: 8 data bits (LSB first). The
baud rate is fixed at 1/12 the f
OSC
.
Figure 27, page 66 shows a simplified functional
diagram of the serial port in Mode 0, and associat-
ed timing.
Transmission is initiated by any instruction that
uses SBUF as a destination register. The “WRITE
to SBUF” signal at S6P2 also loads a '1' into the
9th position of the transmit shift register and tells
the TX Control block to commence a transmission.
The internal timing is such that one full machine
cycle will elapse between “WRITE to SBUF” and
activation of SEND.
SEND enables the output of the shift register to the
alternate out-put function line of RxD and also en-
able SHIFT CLOCK to the alternate output func-
tion line of TxD. SHIFT CLOCK is low during S3,
S4, and S5 of every machine cycle, and high dur-
ing S6, S1, and S2. At S6P2 of every machine cy-
cle in which SEND is active, the contents of the
transmit shift are shifted to the right one position.
As data bits shift out to the right, zeros come in
from the left. When the MSB of the data byte is at
the output position of the shift register, then the '1'
that was initially loaded into the 9th position, is just
to the left of the MSB, and all positions to the left
of that contain zeros. This condition flags the TX
Control block to do one last shift and then deacti-
vate SEND and set T1. Both of these actions occur
at S1P1. Both of these actions occur at S1P1 of
the 10th machine cycle after “WRITE to SBUF.”
Reception is initiated by the condition REN = 1 and
R1 = 0. At S6P2 of the next machine cycle, the RX
Control unit writes the bits 11111110 to the receive
shift register, and in the next clock phase activates
RECEIVE.
RECEIVE enables SHIFT CLOCK to the alternate
output function line of TxD. SHIFT CLOCK makes
transitions at S3P1 and S6P1 of every machine
cycle in which RECEIVE is active, the contents of
the receive shift register are shifted to the left one
position. The value that comes in from the right is
the value that was sampled at the RxD pin at S5P2
of the same machine cycle.
As data bits come in from the right, '1s' shift out to
the left. When the '0' that was initially loaded into
the right-most position arrives at the left-most po-
sition in the shift register, it flags the RX Control
block to do one last shift and load SBUF. At S1P1
of the 10th machine cycle after the WRITE to
SCON that cleared RI, RECEIVE is cleared as RI
is set.
More About Mode 1.
Ten bits are transmitted
(through TxD), or received (through RxD): a start
Bit (0), 8 data bits (LSB first). and a Stop Bit (1). On
receive, the Stop Bit goes into RB8 in SCON. In
the uPSD325X devices the baud rate is deter-
mined by the Timer 1 or Timer 2 over-flow rate.
Figure 29 shows a simplified functional diagram of
the serial port in Mode 1, and associated timings
for transmit receive.
Transmission is initiated by any instruction that
uses SBUF as a destination register. The “WRITE
to SBUF” signal also loads a '1' into the 9th bit po-
sition of the transmit shift register and flags the TX
Control unit that a transmission is requested.
Transmission actually commences at S1P1 of the
machine cycle following the next rollover in the di-
vide-by-16 counter. (Thus, the bit times are syn-
chronized to the divide-by-16 counter, not to the
“WRITE to SBUF” signal.)
The transmission begins with activation of SEND
which puts the start bit at TxD. One bit time later,
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| uPSD3254B-40T6T | Flash Programmable System Devices with 8032 Microcontroller Core |
| uPSD3254B-40U1T | Flash Programmable System Devices with 8032 Microcontroller Core |
| uPSD3254B-40U6T | Flash Programmable System Devices with 8032 Microcontroller Core |
| UPSD3254BV | Flash Programmable System Devices with 8032 Microcontroller Core |
| UPSD3254A | Flash Programmable System Devices with 8032 Microcontroller Core |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UPSD3254B-24T6 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Devices with 8032 Microcontroller Core and 256Kbit SRAM |
| UPSD3254B-24T6T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Devices with 8032 Microcontroller Core and 256Kbit SRAM |
| UPSD3254B-24U1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Devices with 8032 Microcontroller Core and 256Kbit SRAM |
| UPSD3254B-24U1T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Devices with 8032 Microcontroller Core |
| UPSD3254B-24U6 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Devices with 8032 Microcontroller Core and 256Kbit SRAM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。