參數(shù)資料
型號: uPSD3254B-24T1T
廠商: 意法半導(dǎo)體
英文描述: Flash Programmable System Devices with 8032 Microcontroller Core
中文描述: 閃存可編程系統(tǒng)設(shè)備與8032微控制器內(nèi)核
文件頁數(shù): 53/175頁
文件大小: 1731K
代理商: UPSD3254B-24T1T
53/175
UPSD3254A, UPSD3254BV, UPSD3253B, UPSD3253BV
Watchdog reset pulse width depends on the clock
frequency. The reset period is Tf
OSC
x 12 x 2
22
.
The RESET pulse width is Tf
OSC
x 12 x 2
15
.
Figure 21. RESET Pulse Width
Table 34. Watchdog Timer Clear Register (WDRST: 0A6H)
Table 35. Description of the WDRST Bits
Note: The Watchdog Timer (WDT) is enabled at power-up or reset and must be served or disabled.
7
6
5
4
3
2
1
0
Reserved
WDRST6
WDRST5
WDRST4
WDRST3
WDRST2
WDRST1
WDRST0
Bit
Symbol
Function
7
Reserved
6 to 0
WDRST6 to
WDRST0
To reset watchdog timer, write any value beteen 00h and 7Eh to this register.
This value is loaded to the 7 most significant bits of the 22-bit counter.
For example: MOV WDRST,#1EH
Reset period
(1.258 second at 40Mhz)
(about 6.291 seconds at 8Mhz)
Reset pulse width (about 10ms at 40Mhz, about 50ms at 8Mhz)
AI06823
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參數(shù)描述
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