參數(shù)資料
型號(hào)： UPD789132GS-XXX
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, MICROCONTROLLER, PDSO30
封裝： 0.300 INCH, SHRINK, PLASTIC, SOP-30
文件頁(yè)數(shù)： 36/54頁(yè)
文件大小： 481K
代理商： UPD789132GS-XXX
Data Sheet U13025EJ2V0DS00
39
PD789121, 789122, 789124, 789131, 789132, 789134
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = –40 to +85
°°°°C)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Data retention
supply voltage
VDDDR
1.8
5.5
V
Release signal
set time
tSREL
0
s
Release by RESET
2
7/fCC
s
Oscillation
stabilization wait
time
Note
tWAIT
Release by interrupt request
2
7/fCC
s
Note
The oscillation stabilization wait time is the period during which the CPU operation is stopped to avoid
unstable operation at the beginning of oscillation.
Remark
fCC: System clock oscillation frequency
Data Retention Timing (STOP mode release by RESET)
VDD
Data retention mode
STOP mode
HALT mode
Internal reset operation
Operating mode
tSREL
tWAIT
STOP instruction execution
VDDDR
RESET
Data Retention Timing (Standby release signal: STOP mode release by interrupt signal)
VDD
Data retention mode
STOP mode
HALT mode
Operating mode
tSREL
tWAIT
STOP instruction execution
VDDDR
Standby release signal
(interrupt request)
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