參數(shù)資料
型號(hào)： UPD789132GS-XXX
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, MICROCONTROLLER, PDSO30
封裝： 0.300 INCH, SHRINK, PLASTIC, SOP-30
文件頁(yè)數(shù)： 24/54頁(yè)
文件大?。?/td> 481K
代理商： UPD789132GS-XXX
Data Sheet U13025EJ2V0DS00
28
PD789121, 789122, 789124, 789131, 789132, 789134
Flag
Mnemonic
Operand
Byte
Clock
Operation
ZAC CY
saddr. bit
3
6
(saddr. bit)
← 1
sfr. bit
3
6
sfr. bit
← 1
A. bit
2
4
A. bit
← 1
PSW. bit
3
6
PSW. bit
← 1× × ×
SET1
[HL]. bit
2
10
(HL) . bit
← 1
saddr. bit
3
6
(saddr. bit)
← 0
sfr. bit
3
6
sfr. bit
← 0
A. bit
2
4
A. bit
← 0
PSW. bit
3
6
PSW. bit
← 0× × ×
CLR1
[HL]. bit
2
10
(HL) . bit
← 0
SET1
CY
1
2
CY
← 11
CLR1
CY
1
2
CY
← 00
NOT1
CY
1
2
CY
← CY
×
CALL
!addr16
3
6
(SP – 1)
← (PC + 3)H,(SP – 2) ← (PC + 3)L,
PC
← addr16, SP ← SP – 2
CALLT
[addr5]
1
8
(SP – 1)
← (PC + 1)H,(SP – 2) ← (PC + 1)L,
PCH
← (00000000, addr5 + 1),
PCL
← (00000000, addr5),
SP
← SP – 2
RET
1
6
PCH
← (SP + 1), PCL ← (SP),
SP
← SP + 2
RETI
1
8
PCH
← (SP + 1), PCL ← (SP),
PSW
← (SP + 2), SP ← SP + 3,
NMIS
← 0
RR R
PSW
1
2
(SP – 1)
← PSW, SP ← SP – 1
PUSH
rp
1
4
(SP – 1)
← rpH, (SP – 2) ← rpL,
SP
← SP – 2
PSW
1
4
PSW
← (SP), SP ← SP + 1
R R R
POP
rp
1
6
rpH
← (SP + 1), rpL ← (SP),
SP
← SP + 2
SP, AX
2
8
SP
← AX
MOVW
AX, SP
2
6
AX
← SP
!addr16
3
6
PC
← addr16
$addr16
2
6
PC
← PC + 2 + jdisp8
BR
AX
1
6
PCH
← A, PCL ← X
Remark
One instruction clock cycle is one cycle of the CPU clock (fCPU), selected by the processor clock control
register (PCC).
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