參數(shù)資料
型號(hào)： UPD789132GS-XXX
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, MICROCONTROLLER, PDSO30
封裝： 0.300 INCH, SHRINK, PLASTIC, SOP-30
文件頁數(shù)： 22/54頁
文件大小： 481K
代理商： UPD789132GS-XXX
Data Sheet U13025EJ2V0DS00
27
PD789121, 789122, 789124, 789131, 789132, 789134
Flag
Mnemonic
Operand
Byte
Clock
Operation
ZAC CY
A, #byte
2
4
A
← A ∨ byte
×
saddr, #byte
3
6
(saddr)
← (saddr) ∨ byte
×
A, r
2
4
A
← A ∨ r×
A, saddr
2
4
A
← A ∨ (saddr)
×
A, !addr16
3
8
A
← A ∨ (addr16)
×
A, [HL]
1
6
A
← A ∨ (HL)
×
OR
A, [HL + byte]
2
6
A
← A ∨ (HL + byte)
×
A, #byte
2
4
A
← A ∨ byte
×
saddr, #byte
3
6
(saddr)
← (saddr) ∨ byte
×
A, r
2
4
A
← A ∨ r×
A, saddr
2
4
A
← A ∨ (saddr)
×
A, !addr16
3
8
A
← A ∨ (addr16)
×
A, [HL]
1
6
A
← A ∨ (HL)
×
XOR
A, [HL + byte]
2
6
A
← A ∨ (HL + byte)
×
A, #byte
2
4
A – byte
×
saddr, #byte
3
6
(saddr) – byte
×
A, r
2
4
A – r
×
A, saddr
2
4
A – (saddr)
×
A, !addr16
3
8
A – (addr16)
×
A, [HL]
1
6
A – (HL)
×
CMP
A, [HL + byte]
2
6
A – (HL + byte)
×
ADDW
AX, #word
3
6
AX, CY
← AX + word
×
SUBW
AX, #word
3
6
AX, CY
← AX – word
×
CMPW
AX, #word
3
6
AX – word
×
r2
4
r
← r + 1
×
INC
saddr
2
4
(saddr)
← (saddr) + 1
×
r2
4
r
← r – 1
×
DEC
saddr
2
4
(saddr)
← (saddr) – 1
×
INCW
rp
1
4
rp
← rp + 1
DECW
rp
1
4
rp
← rp – 1
ROR
A, 1
1
2
(CY, A7
← A0, Am – 1 ← Am) × 1×
ROL
A, 1
1
2
(CY, A0
← A7, Am + 1 ← Am) × 1×
RORC
A, 1
1
2
(CY
← A0, A7 ← CY, Am – 1 ← Am) × 1×
ROLC
A, 1
1
2
(CY
← A7, A0 ← CY, Am + 1 ← Am) × 1×
Remark
One instruction clock cycle is one cycle of the CPU clock (fCPU), selected by the processor clock control
register (PCC).
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