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參數(shù)資料
| 型號： | UPD77114GC-XXX-9EU |
| 廠商： | NEC Corp. |
| 英文描述： | MOS INTEGRATED CIRCUIT |
| 中文描述： | 馬鞍山集成電路 |
| 文件頁數(shù)： | 48/62頁 |
| 文件大?。?/td> | 352K |
| 代理商： | UPD77114GC-XXX-9EU |
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Data Sheet U14373EJ3V0DS
48
μ
PD77113A, 77114
μ
PD77113A, 77114
Caution If noise is superimposed on the serial clock, the serial interface may be deadlocked. Bear in
mind the following points when designing your system:
Reinforce the wiring for power supply and ground (if noise is superimposed on the power and
ground lines, it has the same effect as if noise were superimposed on the serial clock).
Shorten the wiring between the device's SCK1 and SCK2 pins, and clock supply source.
Do not cross the signal lines of the serial clock with any other signal lines. Do not route the
serial clock line in the vicinity of a line through which a high alternating current flows.
Supply the clock to the SCK1 and SCK2 pins of the device from the clock source on a one-to-
one basis. Do not supply clock to several devices from one clock source.
Exercise care that the serial clock does not overshoot or undershoot. In particular, make sure
that the rising and falling of the serial clock waveform are clear.
Make sure that the serial clock
rises and falls linearly.
The serial clock must not bound. Noise
must not be superimposed on the serial clock.
The serial clock must not rise or
fall step-wise.
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