- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379503 > UPD77114GC-XXX-9EU (NEC Corp.) MOS INTEGRATED CIRCUIT PDF資料下載
參數(shù)資料
| 型號： | UPD77114GC-XXX-9EU |
| 廠商： | NEC Corp. |
| 英文描述： | MOS INTEGRATED CIRCUIT |
| 中文描述： | 馬鞍山集成電路 |
| 文件頁數(shù)： | 20/62頁 |
| 文件大小： | 352K |
| 代理商： | UPD77114GC-XXX-9EU |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁當(dāng)前第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁
Data Sheet U14373EJ3V0DS
20
μ
PD77113A, 77114
3. CLOCK GENERATOR
The clock generator generates an internal system clock based on the external clock input from the CLKIN pin and
supplies the generated clock to the internal units of the DSP.
For details of how to set the PLL multiple, refer to
4.2 Initializing PLL
, and
8.1 Clock Control Options
.
Stop mode
PLL control circuit
Output divider
Halt divider
Halt mode
Internal
system clock
×
m
CLKOUT
CLKIN
÷
n
÷
l
4. RESET FUNCTION
When a low level of a specified width is input to the RESET pin, the device is initialized.
4.1 Hardware Reset
If the RESET pin is asserted active (low level) for a specified period, the internal circuitry of the DSP is initialized.
If the RESET pin is then deasserted inactive (high level), boot processing of the instruction RAM is performed
according to the status of the port pins (P0 and P1). After boot processing, processing is executed starting from the
instruction at address 0x200 of instruction memory (reset entry). In addition, a self-check is performed by the internal
data RAM at the same time as the boot processing. This check takes about 20 ms (at 50 MHz operation, the length
of this period is in inverse proportion to the operating frequency.)
On power application, the RESET pin must be asserted active (low level) after 4 input clocks have been input with
the RESET pin in the inactive status (high level), after the supply voltage has reached the level of the operating
voltage. In other words, no power-ON reset function is available. On power application, the PLL must be initialized.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| UPD77113AF1-XXX-CN1 | MOS INTEGRATED CIRCUIT |
| UPD77113A | MOS INTEGRATED CIRCUIT |
| UPD77114 | MOS INTEGRATED CIRCUIT |
| UPD7720AC | QUARTERLY MICROPROCESSOR/MICROCOMPUTER RELIABILITY REPORT |
| UPD77210 | 16-BIT FIXED-POINT DIGITAL SIGNAL PROCESSOR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UPD7759C | 制造商: 功能描述: 制造商:undefined 功能描述: 制造商:Panasonic Industrial Company 功能描述:IC |
| UPD780023AGB-G43-8EU-X3-A | 制造商:Renesas Electronics Corporation 功能描述: |
| UPD780023AGB-G44-8EU-E3-A | 制造商:Renesas Electronics Corporation 功能描述: |
| UPD780023AGC-107-8BS-A | 制造商:Renesas Electronics Corporation 功能描述:NECUPD780023AGC-107-8BS-A MASK ROM DEVIC |
| UPD780023AGK-C74-9ET-A | 制造商:Renesas Electronics Corporation 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。