參數(shù)資料
型號(hào)： UPD77114GC-XXX-9EU
廠商： NEC Corp.
英文描述： MOS INTEGRATED CIRCUIT
中文描述： 馬鞍山集成電路
文件頁(yè)數(shù)： 40/62頁(yè)
文件大?。?/td> 352K
代理商： UPD77114GC-XXX-9EU
Data Sheet U14373EJ3V0DS
40
μ
PD77113A, 77114
μ
PD77113A, 77114
AC Characteristics (T
A
=
40 to +85
°
C, with IV
DD
and EV
DD
within recommended operating condition range)
Clock
Timing requirements
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
25
ns
IV
DD
= 1.8
to 2.7 V
25
×
m
50
×
m
ns
CLKIN cycle time
Note 1
t
cCX
PLL lock
range
Note 2
IV
DD
= 2.3
to 2.7 V
10
×
m
50
×
m
ns
CLKIN high-level width
t
wCXH
12.5
ns
CLKIN low-level width
t
wCXL
12.5
ns
CLKIN rise/fall time
t
rfCX
5
ns
IV
DD
= 1.8 to 2.7 V
25
ns
Internal clock cycle time
requirements
Note 3
t
cC (R)
IV
DD
= 2.3 to 2.7 V
13.3
ns
Notes 1.
m: Multiple, n: Division ratio
2.
This is the range in which the PLL is locked (stably oscillates). Input t
cCX
within this range.
3.
Input t
cCX
so that the value of (t
cCX
÷
m
×
n) satisfies this condition.
Switching characteristics
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
During normal operation
t
cCX
×
n
÷
m
ns
Internal clock cycle
Note
t
cC
In HALT mode
t
cCX
×
n
÷
m
×
l
ns
CLKOUT cycle time
t
cCO
t
cC
ns
n = 1, or even number
t
cC
÷
2
3
ns
During
normal
operation
n = odd number
(other than 1)
t
cC
÷
n
÷
2
3
ns
CLKOUT width
t
wCO
In HALT mode
t
cC
÷
n
÷
2
3
ns
CLKOUT rise/fall time
t
rfCO
5
ns
IV
DD
= 1.8 to 2.7 V
20
ns
CLKOUT delay time
t
dCO
IV
DD
= 2.3 to 2.7 V
15
ns
Note
m: Multiple, n: Division ratio, l: HALT division ratio
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