參數(shù)資料
型號(hào)： UPD75P3018AGK-9EU
廠商： NEC Corp.
元件分類： 圓形連接器
英文描述： Circular Connector; No. of Contacts:56; Series:MS27467; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:25; Circular Contact Gender:Pin; Circular Shell Style:Straight Plug; Insert Arrangement:25-4 RoHS Compliant: No
中文描述： 4位單片機(jī)
文件頁(yè)數(shù)： 40/64頁(yè)
文件大?。?/td> 356K
代理商： UPD75P3018AGK-9EU
PD75P3018A
45
Data Sheet U11917EJ2V0DS00
Data retention characteristics of data memory in STOP mode and at low supply voltage (TA = –40 to +85
°C)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Data retention power
VDDDR
1.8
5.5
V
supply voltage
Release signal setup time
tSREL
0
s
Oscillation stabilization
tWAIT
Released by RESET
215/fX
ms
wait timeNote 1
Released by interrupt request
Note 2
ms
Notes 1. The oscillation stabilization wait time is the time during which the CPU stops operating to prevent unstable
operation when oscillation is started.
2. Set by the basic interval timer mode register (BTM). (Refer to the table below.)
Wait Time
BTM3
BTM2
BTM1
BTM0
fX = 4.19 MHz
fX = 6.0 MHz
–0
00
220/fX (approx. 250 ms) 220/fX (approx. 175 ms)
–0
11
217/fX (approx. 31.3 ms) 217/fX (approx. 21.8 ms)
–1
01
215/fX (approx. 7.81 ms) 215/fX (approx. 5.46 ms)
–1
11
213/fX (approx. 1.95 ms) 213/fX (approx. 1.37 ms)
Data Retention Timing (standby release signal: when STOP mode released by interrupt signal)
STOP mode
VDD
Operation mode
Internal reset operation
HALT mode
Data retention mode
tSREL
tWAIT
STOP instruction execution
RESET
VDDDR
STOP mode
VDD
Operation mode
HALT mode
Data retention mode
tSREL
tWAIT
STOP instruction execution
Standby release signal
(interrupt request)
VDDDR
Data Retention Timing (when STOP mode released by RESET)
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