參數(shù)資料
型號(hào)： UPD75P3018AGK-9EU
廠商： NEC Corp.
元件分類： 圓形連接器
英文描述： Circular Connector; No. of Contacts:56; Series:MS27467; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:25; Circular Contact Gender:Pin; Circular Shell Style:Straight Plug; Insert Arrangement:25-4 RoHS Compliant: No
中文描述： 4位單片機(jī)
文件頁數(shù)： 33/64頁
文件大小： 356K
代理商： UPD75P3018AGK-9EU
PD75P3018A
39
Data Sheet U11917EJ2V0DS00
AC Characteristics (TA = –40 to +85
°C, VDD = 1.8 to 5.5 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
CPU clock cycle time Note 1
tCY
Operation with
VDD = 2.7 to 5.5 V
0.67
64
s
(minimum instruction execution
main system clock
0.95
64
s
time = 1 machine cycle)
Operation with subsystem clock
114
122
125
s
TI0, TI1, TI2 input frequency
fTI
VDD = 2.7 to 5.5 V
0
1.0
MHz
0
275
kHz
TI0, TI1, TI2 input high-/
tTIH, tTIL
VDD = 2.7 to 5.5 V
0.48
s
low-level width
1.8
s
Interrupt input high-/low-level tINTH, tINTL INT0
IM02 = 0
Note 2
s
width
IM02 = 1
10
s
INT1, 2, 4
10
s
KR0-7
10
s
RESET low-level width
tRSL
10
s
Notes 1. The cycle time (minimum instruc-
tion execution time) of the CPU
clock (
Φ) is determined by the
oscillation frequency of the
connected
resonator
(and
external clock), the system clock
control register (SCC), and
processor clock control register
(PCC).
The figure on the right shows the
supply voltage VDD vs. cycle time
tCY characteristics when the
device operates with the main
system clock.
2. 2tCY or 128/fX depending on the
setting of the interrupt mode
register (IM0).
Operation
guaranteed range
Supply voltage
VDD [V]
0123456
0.5
1
2
3
4
5
6
60
64
Cycle
time
t
CY
[
s]
tCY vs VDD
(with main system clock)
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