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參數(shù)資料
| 型號(hào)： | UPD7554AG |
| 廠商： | NEC Corp. |
| 英文描述： | 4-BIT SINGLE-CHIP MICROCOMPUTER |
| 中文描述： | 4位單片機(jī) |
| 文件頁數(shù)： | 26/64頁 |
| 文件大小： | 991K |
| 代理商： | UPD7554AG |
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26
μ
PD7554A, 7554A(A)
The INTT RQF is set when a timer overflow occurs and is reset by the SKI or TIMER instruction.
The INT0/S request flag functions in the following two ways according to the setting of the SM3:
(1) SM3 = 0
The INTS is validated. The request flag INT0/S RQF is set when the INTS signal to indicate the termination of 8-
bit serial data transfer is issued. The flag is reset when the SKI or SIO instruction is executed.
(2) SM3 = 1
The IN0 is validated. The request flag INT0/S RQF is set when the leading edge signal enters the INT0/P00 pin.
The flag is reset when the SKI instruction is executed.
The OR output of each test request flag is used to cancel the standby mode (STOP/HALT mode). If one or more
request flags are set in the standby mode, the standby mode is cancelled.
The RESET signal cancels every request flag and the SM3. In the reset initial status, the INTS is selected and the
INT0 input is disabled.
Fig. 2-17 Test Control Circuit Block Diagram
INTS
TEST RQF
CONTROL
SKI
Note
TIMER
Note
S
R
INTT
RQF
Q
S
R
INT0/S
RQF
Q
NONSYNC
EDGE GATE
NONSYNC
EDGE GATE
SM3
OPL
Note
SIO
Note
INT0
INTT
STANDBY
RELEASE
Internal Bus
Note
Instruction execution
Remark
SM3 is bit 3 of the shift mode register.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UPD7554AG-597-E2 | 制造商:Renesas Electronics Corporation 功能描述: |
| UPD7554AG-597-E2-A | 制造商:Renesas Electronics Corporation 功能描述: |
| UPD7554AG-603-E2 | 制造商:Renesas Electronics Corporation 功能描述: |
| UPD7554AG-603-E2-A | 制造商:Renesas Electronics Corporation 功能描述: |
| UPD7554AG-611-E2 | 制造商:Renesas Electronics Corporation 功能描述: |
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