參數(shù)資料
型號(hào)： UPD7554AG
廠商： NEC Corp.
英文描述： 4-BIT SINGLE-CHIP MICROCOMPUTER
中文描述： 4位單片機(jī)
文件頁(yè)數(shù)： 24/64頁(yè)
文件大小： 991K
代理商： UPD7554AG
24
μ
PD7554A, 7554A(A)
The serial interface sets serial data for transmission in the shift register using the TAMSIO instruction and starts
the transfer using the SIO instruction. To recognize the termination of one-byte transfer, check the test request flag
INT0/S RQF using the corresponding instruction.
The serial interface starts serial data reception, using the SIO instruction, checks the termination of one-byte
transfer using the instruction, and then receives data from the shift register by executing the TSIOAM instruction.
Two types of serial clock sources are available: one is the system clock
φ
and the other is the external clock (SCK
input). They are selected respectively by bits 2 and 1 (SM2 and SM1) of the shift mode register.
When the system clock
φ
is selected and the SIO instruction is executed, the clock pulse is supplied to the serial
interface as a serial clock to control serial data input/output and is output from the SCK pin.
When the system clock
φ
pulse is supplied eight times, the supply to the serial interface is automatically stopped
and the SCK output remains high. Since serial data input/output stops automatically after transfer of one byte. The
programmer does not need to control the serial clock. In this case, the transfer speed is determined by the system
clock frequency.
In this mode, it is possible to read receive data (by the TSIOAM instruction) and write data (by the TAMSIO
instruction) from and to the shift register only by waiting for 6 machine cycles after execution of the SIO instrucction
on the program without waiting until the INT0/S RQF is set.
Fig. 2-15 TAMSIO/TSIOAM Instruction Execution Timing
SCK
SIO
TAMSIO
TSIOAM
Wait (6 Machine Cycle)
Instruction Execution
Machine Cycle
When the external clock (SCK input) is selected, the interface inputs serial clock pulses from the SCK input. When
an external serial clock pulse is input eight times, the INT0/S RQF is set and the termination of one-byte transfer
can be recognized. However, the eight serial clocks to be input must be counted on the side of the external clock
source because serial clock disable control is not performed internally. The transfer speed is determined by the
external serial clock within the range from DC to the maximum value limited by the standard.
When the external clock is used, the SIO, TAMSIO, or TSIOAM instruction the execution must be executed while
the serial clock pulse SCK is high. If such an instruction is executed while the SCK is rising or falling or is low, the
function of the instruction is not guaranteed.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
UPD7554AG-597-E2 制造商:Renesas Electronics Corporation 功能描述:
UPD7554AG-597-E2-A 制造商:Renesas Electronics Corporation 功能描述:
UPD7554AG-603-E2 制造商:Renesas Electronics Corporation 功能描述:
UPD7554AG-603-E2-A 制造商:Renesas Electronics Corporation 功能描述:
UPD7554AG-611-E2 制造商:Renesas Electronics Corporation 功能描述:
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