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參數(shù)資料
| 型號(hào)： | UPD754244GS-XXX-GJG |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PDSO20 |
| 封裝： | 0.300 INCH, 0.65 MM PITCH, PLASTIC, SSOP-20 |
| 文件頁(yè)數(shù)： | 8/90頁(yè) |
| 文件大?。?/td> | 602K |
| 代理商： | UPD754244GS-XXX-GJG |
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PD754144, 754244
14
Data Sheet U10040EJ2V1DS
4.2 Setting Method of Stack Bank Select Register (SBS)
Switching between the Mk I mode and Mk II mode can be done by the SBS. Figure 4-1 shows the format.
The SBS is set by a 4-bit memory manipulation instruction.
When using the Mk I mode, the SBS must be initialized to 1000B at the beginning of a program. When using
the Mk II mode, it must be initialized to 0000B.
Figure 4-1. Stack Bank Select Register Format
Caution Because SBS. 3 is set to “1” after a RESET signal is generated, the CPU operates in the
Mk I mode. When executing an instruction in the Mk II mode, set SBS. 3 to “0” to select
the Mk II mode.
Address
Stack area specification
Symbol
SBS
F84H
SBS3
SBS2 SBS1
SBS0
32
1
0
Memory bank 0
Mk II mode
Mk I mode
Other than above setting prohibited
Mode switching specification
0 must be set in the bit 2 position
0
1
0
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