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參數(shù)資料
| 型號(hào)： | UPD754244GS-XXX-GJG |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PDSO20 |
| 封裝： | 0.300 INCH, 0.65 MM PITCH, PLASTIC, SSOP-20 |
| 文件頁(yè)數(shù)： | 61/90頁(yè) |
| 文件大?。?/td> | 602K |
| 代理商： | UPD754244GS-XXX-GJG |
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PD754144, 754244
62
Data Sheet U10040EJ2V1DS
PD754244
AC Characteristics (TA = –40 to +85
°C, VDD = 1.8 to 6.0 V)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
CPU clock cycle time Note 1
tCY
VDD = 1.8 to 2.0 V
1.9
64.0
s
(Minimum instruction execution
VDD = 2.0 to 2.7 V
0.95
64.0
s
time = 1 machine cycle)
VDD = 2.7 to 6.0 V
0.67
64.0
s
Interrupt input high- and
tINTH, tINTL
INT0
IM02 = 0
Note 2
s
low-level width
IM02 = 1
10
s
KR4 to KR7
10
s
RESET low-level width
tRSL
10
s
Notes 1.
The CPU clock (
Φ) cycle time (minimum
instruction execution time) is determined
by the oscillation frequency of the con-
nected resonator (or external clock) and
the processor clock control register (PCC).
The figure on the right shows the cycle
time tCY characteristics against the supply
voltage VDD when the system clock is used.
2.
2tCY or 128/fX depending on the setting of
the interrupt mode register (IM0).
0.5
0
Supply voltage VDD (V)
12
3456
1
2
1.9
0.95
0.67
2.7
3
4
5
6
60
64
(During system clock operation)
tCY vs. VDD
Operation guranteed range
1.8
Cycle
time
t
CY
(
s)
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