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參數(shù)資料
| 型號： | UPD754244GS-XXX-GJG |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PDSO20 |
| 封裝： | 0.300 INCH, 0.65 MM PITCH, PLASTIC, SSOP-20 |
| 文件頁數(shù)： | 44/90頁 |
| 文件大?。?/td> | 602K |
| 代理商： | UPD754244GS-XXX-GJG |
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PD754144, 754244
47
Data Sheet U10040EJ2V1DS
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Instruction
Number
Addressing
Mnemonic
Operand
of machine
Operation
Skip condition
group
of bytes
cycles
area
Interrupt
EI
2
IME (IPS.3)
← 1
control
instructions
IE
×××
22
IE
××× ← 1
DI
2
IME (IPS.3)
← 0
IE
×××
22
IE
××× ← 0
Input/output
INNote 1
A, PORTn
2
A
← PORTn
(n = 3, 6, 7, 8)
instructions
OUTNote 1
PORTn, A
2
PORTn
← A
(n = 3, 6, 8)
CPU control
HALT
2
Set HALT Mode (PCC.2
← 1)
instructions
STOP
2
Set STOP Mode (PCC.3
← 1)
NOP
1
No Operation
Special
SEL
RBn
2
RBS
← n
(n = 0-3)
instructions
MBn
2
MBS
← n
(n = 0, 4, 15)
GETINotes 2, 3 taddr
1
3
When TBR instruction
*10
PC11–0
← (taddr) 3–0 + (taddr+1)
When TCALL instruction
(SP–4) (SP–1) (SP–2)
← PC11–0
(SP–3)
← MBE, RBE, 0, 0
PC11–0
← (taddr) 3–0 + (taddr+1)
SP
← SP–4
When instruction other than TBR and
Depending on
TCALL instructions
the reference
(taddr) (taddr+1) instruction is executed.
instruction
3 When TBR instruction
*10
PC11–0
← (taddr) 3–0 + (taddr+1)
4 When TCALL instruction
(SP–6) (SP–3) (SP–4)
← PC11–0
(SP–5)
← 0, 0, 0, 0
(SP–2)
← ×, ×, MBE, RBE
PC11–0
← (taddr) 3–0 + (taddr+1)
SP
← SP–6
3 When instruction other than TBR and
Depending on
TCALL instructions
the reference
(taddr) (taddr+1) instruction is executed.
instruction
Notes 1.
While the IN instruction and OUT instruction are being executed, MBE must be set to 0, or MBE must
be set to 1 and MBS must be set to 15.
2.
The TBR and TCALL instructions are the table definition assembler pseudo instructions of the GETI
instruction.
3.
The above operations in the double boxes can be performed only in the Mk II mode. The other
operations can be performed only in the Mk I mode.
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