參數(shù)資料
型號： UPD754244GS-XXX-GJG
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PDSO20
封裝： 0.300 INCH, 0.65 MM PITCH, PLASTIC, SSOP-20
文件頁數(shù)： 28/90頁
文件大?。?/td> 602K
代理商： UPD754244GS-XXX-GJG
PD754144, 754244
32
Data Sheet U10040EJ2V1DS
10. RESET FUNCTION
10.1 Configuration and Operation Status of RESET Function
There are three kinds of reset input: the external reset signal (RESET), the reset signal sent from the basic
interval/watchdog timer, and the reset signal generated by a falling edge signal from KRn in the STOP mode. When
any of these reset signals is input, an internal reset signal is generated. The configuration is shown in Figure
10-1.
Figure 10-1. Configuration of Reset Function
VDD
Mask option
Output buffer
KRREN
RESET
QR
S
Q
S
R
Q
S
R
Instruction
Interrupt
STOP mode
KRF
WDF
Watchdog timer overflow
Internal reset signal
Instruction
One-shot pulse generator
Falling edge detector
VDD
Mask option
P70/KR4
P71/KR5
P72/KR6
P73/KR7
Internal
bus
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