參數(shù)資料
型號： UPD72042BGT
廠商： NEC Corp.
英文描述： LSI DEVICES FOR Inter Equipment BusTM (IEBusTM) PROTOCOL CONTROL
中文描述： LSI器件間設(shè)備BusTM（IEBusTM）協(xié)議控制
文件頁數(shù)： 48/92頁
文件大?。?/td> 541K
代理商： UPD72042BGT
μ
PD72042A, 72042B
48
DATA SHEET S13990EJ2V0DS00
Table 4-2 MARC Return Codes for Master Transmission
MARC
Description
0000
1. Meaning
: Master transmission is started.
2. Occurrence condition
: This return code is issued when the master address field in a communication
frame has been transmitted, and the unit has won the arbitration to become the master unit.
0001
1. Meaning
: Master transmission data is not available.
2. Occurrence condition
: This return code is issued if the next transmission data is not set in TBF during
master transmission.
3. Microcomputer processing
: If data consisting of one or more bytes is not set in TBF within the time
below, transmission may be terminated prior to its completion.
Transmission data setting time:
Approx. 1570
μ
s (mode 0)
Approx. 390
μ
s (mode 1)
0010
1. Meaning
: Master transmission was terminated normally.
2. Occurrence condition
: This return code is issued when as much data as the amount specified in the
data-length field has been transmitted normally. In this case, the MARQ flag of the FLG register changes
from 1 to 0.
0011
1. Meaning
: Master transmission was aborted.
2. Occurrence condition
: This return code is issued in any of the following cases. In each case, the MARQ
flag of the FLG register changes from 1 to 0.
When the unit has lost the arbitration to become the master unit.
When a transmission is stopped because the NAK is returned from the slave unit at the end of the slave
address field, the control field, or the data-length field of a communication frame (excluding the broadcast).
When a communication is terminated prior to the transmission of as much data as the amount specified
in the data-length field of a communication frame.
(b) Master reception
Master reception is performed when the microcomputer performs the setting below.
Master reception setting
1 In the low-order 4 bits of the MCR register, control bits (0000, 0011, 0100, 0101, 0110, or 0111) are set
for slave-to-master data transfer.
2 In COMC of the CMR register, a command (1000 or 1001) for requesting master communication is set.
Table 4-3 indicates the MARC return codes for master reception.
相關(guān)PDF資料
PDF描述
UPD72042A LSI DEVICES FOR Inter Equipment BusTM (IEBusTM) PROTOCOL CONTROL
UPD72042AGT LSI DEVICES FOR Inter Equipment BusTM (IEBusTM) PROTOCOL CONTROL
UPD72042B LSI DEVICES FOR Inter Equipment BusTM (IEBusTM) PROTOCOL CONTROL
UPD72065GC Floppy Disk Controller
UPD72065BGC-3B6 RTS Series - Econoline Unregulated DC-DC Converters; Input Voltage (Vdc): 24V; Output Voltage (Vdc): 15V; Power: 2W; Assembly; High Power Density; Optional Continuous Short Circuit Protected; Efficiency to 85%
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
UPD72042BGT-A 制造商:Renesas Electronics 功能描述:LSI Device 16-Pin SOP 制造商:Renesas Electronics 功能描述:LSI Device 16-Pin SOP Cut Tape
UPD72042GT(A) 制造商:Renesas Electronics Corporation 功能描述:
UPD720902AF5-667-JF2-E3-A 功能描述:IC ADVANCED MEMORY BUFFER D1 RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:* 標(biāo)準(zhǔn)包裝:90 系列:- 應(yīng)用:PCI 至 PCI 橋 接口:PCI 電源電壓:3 V ~ 3.6 V 封裝/外殼:257-LFBGA 供應(yīng)商設(shè)備封裝:257-BGA MICROSTAR（16x16） 包裝:托盤 安裝類型:表面貼裝 產(chǎn)品目錄頁面:882 (CN2011-ZH PDF) 其它名稱:296-19316
UPD72255YF1-GA5-A 制造商:Renesas Electronics Corporation 功能描述:
UPD7225G 制造商:Panasonic Industrial Company 功能描述:IC
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*