參數(shù)資料
型號(hào): UPD72042BGT
廠商: NEC Corp.
英文描述: LSI DEVICES FOR Inter Equipment BusTM (IEBusTM) PROTOCOL CONTROL
中文描述: LSI器件間設(shè)備BusTM(IEBusTM)協(xié)議控制
文件頁(yè)數(shù): 24/92頁(yè)
文件大?。?/td> 541K
代理商: UPD72042BGT
μ
PD72042A, 72042B
24
DATA SHEET S13990EJ2V0DS00
(2) Data read mode
When the C/D pin is set low after register read is selected in control mode, the data read mode is set. In data
read mode, the data in a read register is read on the SO pin upon detecting the falling edge of the SCK pin.
(a)
μ
PD72042A (starting with MSB)
C/D
SCK
SI
A3
A2
A1
A0
×
×
×
D7 D6
D5 D4
D3 D2
D1 D0
SO
State
Control mode
(selection of register read)
Data read mode
Serial clock counter
reset pointer
1
“1”
(b)
μ
PD72042B (starting with LSB)
C/D
SCK
SI
A0
A1
A2
A3
×
×
×
D0 D1
D2 D3
D4 D5
D6 D7
SO
State
Control mode
(selection of register read)
Data read mode
Serial clock counter
reset pointer
“1”
1
Caution When the C/D pin is set high in data read mode, the serial clock counter is reset. Therefore, the
remaining bits of the byte cannot be read; at the next falling edge, read is performed starting from
the next byte in the case of RBF, or from the first bit for other registers.
相關(guān)PDF資料
PDF描述
UPD72042A LSI DEVICES FOR Inter Equipment BusTM (IEBusTM) PROTOCOL CONTROL
UPD72042AGT LSI DEVICES FOR Inter Equipment BusTM (IEBusTM) PROTOCOL CONTROL
UPD72042B LSI DEVICES FOR Inter Equipment BusTM (IEBusTM) PROTOCOL CONTROL
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參數(shù)描述
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