參數(shù)資料
型號(hào)： UPD70F3079YGF-3BA
元件分類(lèi)： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 16 MHz, RISC MICROCONTROLLER, PQFP100
封裝： 14 X 20 MM, PLASTIC, QFP-100
文件頁(yè)數(shù)： 39/54頁(yè)
文件大?。?/td> 529K
代理商： UPD70F3079YGF-3BA
Data Sheet U15183EJ2V0DS
42
PD703078Y, 703079Y, 70F3079Y
(10) I
2C bus mode
(TA = –40 to +85°C, GND0 = GND1 = GND2 = PORTGND = 0 V,
PD703078Y, 703079Y: VDD0 = PORTVDD =
3.5 to 5.5 V,
PD70F3079Y: VDD0 = PORTVDD = 4.0 to 5.5 V) (1/2)
Normal Mode
High-Speed Mode
Parameter
Symbol
MIN.
MAX.
MIN.
MAX.
Unit
SCL0 clock frequency
–
fCLK
0
100
0
400
kHz
Bus-free time (between
stop/start conditions)
<75>
tBUF
4.7
–
1.3
–
s
Hold time
Note 1
<76>
tHD:STA
4.0
–
0.6
–
s
SCL0 clock low-level width
<77>
tLOW
4.7
–
1.3
–
s
SCL0 clock high-level width
<78>
tHIGH
4.0
–
0.6
–
s
Setup time for start/restart
conditions
<79>
tSU:STA
4.7
–
0.6
–
s
CBUS
compatible
master
5.0
–––
s
Data hold
time
I
2C mode
<80>
tHD:DAT
0
Note 2
–
0
Note 2
0.9
Note 3
s
Data setup time
<81>
tSU:DAT
250
–
100
Note 4
–
ns
SDA0 and SCL0 signal rise
time
<82>
tR
–
1000
20 + 0.1Cb
Note 5
300
ns
SDA0 and SCL0 signal fall
time
<83>
tF
–
300
20 + 0.1Cb
Note 5
300
ns
Stop condition setup time
<84>
tSU:STO
4.0
–
0.6
–
s
Pulse width of spike
suppressed by input filter
<85>
tSP
––
050
ns
bus line
–
Cb
–
400
–
400
pF
Notes 1.
At the start condition, the first clock pulse is generated after the hold time.
2.
The system requires a minimum of 300 ns hold time internally for the SDA0 signal (at VIHmin.
. of SCL0
signal) in order to occupy the undefined area at the falling edge of SCL0.
3.
If the system does not extend the SCL0 signal low hold time (tLOW), only the maximum data hold time
(tHD:DAT) needs to be satisfied.
4.
The high-speed mode I
2C bus can be used in the normal-mode I2C bus system. In this case, set the
high-speed mode I
2C bus so that it meets the following conditions.
If the system does not extend the SCL0 signal’s low state hold time:
tHD:DAT
≥ 250 ns
If the system extends the SCL0 signal’s low state hold time:
Transmit the following data bit to the SDA0 line prior to the SCL0 line release (tRmax. + tSU:DAT = 1000
+ 250 = 1250 ns: Normal mode I
2C bus specification).
5.
Cb: Total capacitance of one bus line (unit: pF)
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