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| 型號： | UPD70F3079YGF-3BA |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 16 MHz, RISC MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 20 MM, PLASTIC, QFP-100 |
| 文件頁數(shù)： | 26/54頁 |
| 文件大?。?/td> | 529K |
| 代理商： | UPD70F3079YGF-3BA |
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Data Sheet U15183EJ2V0DS
30
PD703078Y, 703079Y, 70F3079Y
(b) Clock asynchronous
(TA = –40 to +85°C, GND0 = GND1 = GND2 = PORTGND = 0 V,
PD703078Y, 703079Y: VDD0 = PORTVDD =
3.5 to 5.5 V,
PD70F3079Y: VDD0 = PORTVDD = 4.0 to 5.5 V)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
Address setup time (to ASTB
↓)
<10>
tSAST
0.5T – 32
ns
Address hold time (from ASTB
↓)
<11>
tHSTA
0.5T – 22
ns
Delay time from DSTB
↓ to address float
<12>
tFDA
0ns
Data input setup time from address
<13>
tSAID
(2 + n)T – 70
ns
Data input setup time from DSTB
↓
<14>
tSDID
(1 + n)T – 60
ns
Data input setup time from ASTB
↓
<15>
tSASID
(1.5 + n)T – 70
ns
Delay time from ASTB
↓ to DSTB↓
<16>
tDSTD
0.5T – 15
ns
Data input hold time (from DSTB
↑)
<17>
tHDID
0ns
Address output time from DSTB
↑
<18>
tDDA
(1 + i)T – 15
ns
Delay time from DSTB
↑ to ASTB↑
<19>
tDDST1
0.5T – 15
ns
Delay time from DSTB
↑ to ASTB↓
<20>
tDDST2
(1.5 + i)T – 15
ns
DSTB low-level width
<21>
tWDL
(1 + n)T – 35
ns
ASTB high-level width
<22>
tWSTH
T – 15
ns
Data output time from DSTB
↓
<23>
tDDOD
25
ns
Data output setup time (to DSTB
↑)
<24>
tSODD
(1 + n)T – 35
ns
Data output hold time (from DSTB
↑)
<25>
tHDOD
T – 25
ns
<26>
tSAWT1
n
≥ 1
1.5T – 70
ns
WAIT setup time (to address)
<27>
tSAWT2
(1.5 + n)T – 70
ns
<28>
tHAWT1
n
≥ 1
(0.5 + n)T
ns
WAIT hold time (from address)
<29>
tHAWT2
(1.5 + n)T
ns
<30>
tSSTWT1
n
≥ 1T – 55
ns
WAIT setup time (to ASTB
↓)
<31>
tSSTWT2
(1 + n)T – 55
ns
<32>
tHSTWT1
n
≥ 1nT
ns
WAIT hold time (from ASTB
↓)
<33>
tHSTWT2
(1 + n)T
ns
HLDRQ high-level width
<34>
tWHQH
T + 10
ns
HLDAK low-level width
<35>
tWHAL
T – 25
ns
Delay time from HLDAK
↑ to bus output
<36>
tDHAC
0ns
Delay time from HLDRQ
↓ to HLDAK↓
<37>
tDHQHA1
1.5T
(2n + 7.5)T + 25
ns
Delay time from HLDRQ
↑ to HLDAK↑
<38>
tDHQHA2
0.5T
1.5T + 25
ns
Remarks 1. T: 1/fCPU (fCPU: CPU clock frequency)
2. n: Number of wait clocks inserted in the bus cycle.
The sampling timing changes when a programmable wait is inserted.
3. i: Number of idle cycles inserted in the bus cycle.
4. The values in the above specifications are values for when clocks with a 1:1 duty ratio are input
from X1.
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