參數(shù)資料
型號： UPD70F3079YGF-3BA
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 16 MHz, RISC MICROCONTROLLER, PQFP100
封裝： 14 X 20 MM, PLASTIC, QFP-100
文件頁數(shù)： 27/54頁
文件大小： 529K
代理商： UPD70F3079YGF-3BA
Data Sheet U15183EJ2V0DS
31
PD703078Y, 703079Y, 70F3079Y
(c) Clock synchronous
(TA = –40 to +85°C, GND0 = GND1 = GND2 = PORTGND = 0 V,
PD703078Y, 703079Y: VDD0 = PORTVDD =
4.0 to 5.5 V,
PD70F3079Y: VDD0 = PORTVDD = 4.5 to 5.5 V)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
Delay time from CLKOUT
↑ to address
<39>
tDKA
035
ns
Delay time from CLKOUT
↑ to address float <40>
tFKA
–12
15
ns
Delay time from CLKOUT
↓ to ASTB
<41>
tDKST
030
ns
Delay time from CLKOUT
↑ to DSTB
<42>
tDKD
030
ns
Data input setup time (to CLKOUT
↑)
<43>
tSIDK
20
ns
Data input hold time (from CLKOUT
↑)
<44>
tHKID
5ns
Delay time from CLKOUT
↑ to data output
<45>
tDKOD
35
ns
WAIT setup time (to CLKOUT
↓)
<46>
tSWTK
25
ns
WAIT hold time (from CLKOUT
↓)
<47>
tHKWT
5ns
HLDRQ setup time (to CLKOUT
↓)
<48>
tSHQK
20
ns
HLDRQ hold time (from CLKOUT
↓)
<49>
tHKHQ
5ns
Delay time from CLKOUT
↑ to address
float (during bus hold)
<50>
tDKF
19
ns
Delay time from CLKOUT
↑ to HLDAK
<51>
tDKHA
35
ns
Remark
The values in the above specifications are values for when clocks with a 1:1 duty ratio are input from
X1.
(d) Clock synchronous
(TA = –40 to +85°C, GND0 = GND1 = GND2 = PORTGND = 0 V,
PD703078Y, 703079Y: VDD0 = PORTVDD =
3.5 to 5.5 V,
PD70F3079Y: VDD0 = PORTVDD = 4.0 to 5.5 V)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
Delay time from CLKOUT
↑ to address
<39>
tDKA
045
ns
Delay time from CLKOUT
↑ to address float <40>
tFKA
–17
15
ns
Delay time from CLKOUT
↓ to ASTB
<41>
tDKST
035
ns
Delay time from CLKOUT
↑ to DSTB
<42>
tDKD
035
ns
Data input setup time (to CLKOUT
↑)
<43>
tSIDK
20
ns
Data input hold time (from CLKOUT
↑)
<44>
tHKID
5ns
Delay time from CLKOUT
↑ to data output
<45>
tDKOD
45
ns
WAIT setup time (to CLKOUT
↓)
<46>
tSWTK
29
ns
WAIT hold time (from CLKOUT
↓)
<47>
tHKWT
5ns
HLDRQ setup time (to CLKOUT
↓)
<48>
tSHQK
24
ns
HLDRQ hold time (from CLKOUT
↓)
<49>
tHKHQ
5ns
Delay time from CLKOUT
↑ to address
float (during bus hold)
<50>
tDKF
19
ns
Delay time from CLKOUT
↑ to HLDAK
<51>
tDKHA
40
ns
Remark
The values in the above specifications are values for when clocks with a 1:1 duty ratio are input from
X1.
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