
CHAPTER 5 BUS CONTROL FUNCTION
User
’
s Manual U15862EJ3V0UD
281
5.7 Idle State Insertion Function
To facilitate interfacing with low-speed memories, one idle state (TI) can be inserted after the T3 state in the bus
cycle that is executed for each space selected by the chip select function in the multiplex address/data bus mode. In
the separate bus mode, one idle state (TI) can be inserted after the T2 state. By inserting idle states, the data output
float delay time of the memory can be secured during read access (an idle state cannot be inserted during write
access).
Whether the idle state is to be inserted can be programmed by using the bus cycle control register (BCC).
An idle state is inserted for all the areas immediately after system reset.
(1) Bus cycle control register (BCC)
This register can be read or written in 16-bit units.
Cautions 1. The internal ROM, internal RAM, and on-chip peripheral I/O areas are not subject to idle
state insertion.
2. Write to the BCC register after reset, and then do not change the set values. Also, do not
access an external memory area other than the one for this initialization routine until the
initial settings of the BCC register are complete. However, external memory areas whose
initial settings are complete may be accessed.
After reset: AAAAH R/W Address: FFFFF48AH
1
BC31
Note
BCn1
0
1
Not inserted
Inserted
BCC
0
0
1
BC21
Note
0
0
1
BC11
0
0
1
BC01
0
0
8
9
10
11
12
13
Specifies insertion of idle state (n = 0 to 3)
14
15
1
2
3
4
5
6
7
0
CS0
CS3
CSn signal
CS2
CS1
Note
The BC31 and BC21 bits are only valid in the V850ES/KJ1.
Changing these bits has no effect on the operation in the
V850ES/KF1 and V850ES/KG1.
Caution
Be sure to set bits 15, 13, 11, and 9 to 1, and clear bits 14, 12,
10, 8, 6, 4, 2, and 0 to 0.