
38
μ
PD70320
Table 2-8. Number of Clocks (2/10)
Notes 1.
n
≥
1
2.
When IBRK = 1
Byte Processing
Word Processing
Group
Mnemonic
Operands
On-chip RAM
Access Enable
On-chip RAM
Access Disable
On-chip RAM
Access Enable
On-chip RAM
Access Disable
Primitive
block
transfer
CMPM
Note 1
dst-block
src-block
17 + T
17 + T
19 + 2·T
19 + 2·T
16 + (15 + T)·n
16 + (15 + T)·n
16 + (17 + 2·T)·n
16 + (17 + 2·T)·n
LDM
Note 1
src-block
12 + T
12 + T
14 + 2·T
14 + 2·T
16 + (10 + T)·n
16 + (10 + T)·n
16 + (12 + 2·T)·n
16 + (12 + 2·T)·n
STM
Note 1
dst-block
12 + T
10
14 + 2·T
10
16 + (8 + T)·n
16 + (6+ T)·n
16 + (10 + 2·T)·n
16 + (6 + 2·T)·n
Bit field
manipula-
tion
INS
reg8, reg8
63 to 155 (The processing differs among bit lengths.)
reg8, imm4
64 to 156 (The processing differs among bit lengths.)
EXT
reg8, reg8
41 to 121 (The processing differs among bit lengths.)
reg8, imm4
42 to 122 (The processing differs among bit lengths.)
I/O
IN
Note 2
acc, imm8
14 + T
14 + T
16 + 2·T
16 + 2·T
acc, DW
13 + T
13 + T
15 + 2·T
15 + 2·T
OUT
Note 2
imm8, acc
10 + T
10 + T
10 + 2·T
10 + 2·T
DW, acc
9 + T
9 + T
9 + 2·T
9 + 2·T
Primitive
I/O
INM
Note 2
dst-block, DW
19 + 2·T
17 + 2·T
21 + 4·T
17 + 4·T
18 + (13 + 2·T)·n
18 + (11 + 2·T)·n
18 + (15 + 4·T)·n
18 + (11 + 4·T)·n
OUTM
Note 2
DW, src-block
19 + 2·T
17 + 2·T
21 + 4·T
17 + 4·T
18 + (13 + 2·T)·n
18 + (11 + 2·T)·n
18 + (15 + 4·T)·n
18 + (11 + 4·T)·n
Addition/
subtraction
ADD
reg, reg
2
2
2
2
mem, reg
EA + 8 + 2·T
EA + 6 + T
EA + 12 + 4·T
EA + 8 + 2·T
reg, mem
EA + 6 + T
EA + 6 + T
EA + 8 + 2·T
EA + 8 + 2·T
reg, imm
5
5
6
6
mem, imm
EA + 9 + 2·T
EA + 7 + 2·T
EA + 14 + 4·T
EA + 10 + 4·T
acc, imm
5
5
6
6
ADDC
reg, reg
2
2
2
2
mem, reg
EA + 8 + 2·T
EA + 6 + T
EA + 12 + 4·T
EA + 8 + 2·T
reg, mem
EA + 6 + T
EA + 6 + T
EA + 8 + 2·T
EA + 8 + 2·T
reg, imm
5
5
6
6
mem, imm
EA + 9 + 2·T
EA + 7 + 2·T
EA + 14 + 4·T
EA + 10 + 4·T
acc, imm
5
5
6
6