
2
μ
P
MULU
MUL
reg8
mem8
reg16
mem16
reg8
mem8
reg16
mem16
reg16,
(reg16,)
Note
imm8
reg16,
mem16,
imm8
reg16,
(reg16,)
Note
imm16
reg16,
mem16,
imm16
Operation Code
1 1 1 1 0 1 1 0
1 1 1 1 0 1 1 0
1 1 1 1 0 1 1 1
1 1 1 1 0 1 1 1
1 1 1 1 0 1 1 0
1 1 1 1 0 1 1 0
1 1 1 1 0 1 1 1
1 1 1 1 0 1 1 1
0 1 1 0 1 0 1 1
0 1 1 0 1 0 1 1
0 1 1 0 1 0 0 1
0 1 1 0 1 0 0 1
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
Group
Mnemonic
Operand
2
2 to 4
2
2 to 4
2
2 to 4
2
2 to 4
3
3 to 5
4
4 to 6
Bytes
Flags
AC CY V
P
S
Z
AW
←
AL
×
reg8
AH = 0: CY
←
0, V
←
0
AH
≠
0: CY
←
1, V
←
1
AW
←
AL
×
(mem8)
AH = 0: CY
←
0, V
←
0
AH
≠
0: CY
←
1, V
←
1
DW, AW
←
AW
×
reg16
DW = 0: CY
←
0, V
←
0
DW = 1: CY
←
1, V
←
1
DW, AW
←
AW
×
(mem16)
DW = 0: CY
←
0, V
←
0
DW = 1: CY
←
1, V
←
1
AW
←
AL
×
reg8
Extension of AH = AL sign: CY
←
0, V
←
0
Extension of AH
≠
AL sign: CY
←
1, V
←
1
AW
←
AL
×
(mem8)
Extension of AH = AL sign: CY
←
0, V
←
0
Extension of AH
≠
AL sign: CY
←
1, V
←
1
DW, AW
←
AW
×
reg16
Extension of DW = AW sign: CY
←
0, V
←
0
Extension of DW
≠
AW sign: CY
←
1, V
←
1
DW, AW
←
AW
×
(mem16)
Extension of DW = AW sign: CY
←
0, V
←
0
Extension of DW
≠
AW sign: CY
←
1, V
←
1
reg16
←
reg16
×
imm8
Product
≤
16 bits: CY
←
0, V
←
0
Product > 16 bits: CY
←
1, V
←
1
reg16
←
(mem16)
×
imm8
Product
≤
16 bits: CY
←
0, V
←
0
Product > 16 bits: CY
←
1, V
←
1
reg16
←
reg16
×
imm16
Product
≤
16 bits: CY
←
0, V
←
0
Product > 16 bits: CY
←
1, V
←
1
reg16
←
(mem16)
×
imm16
Product
≤
16 bits: CY
←
0, V
←
0
Product > 16 bits: CY
←
1, V
←
1
Operation
Multipli-
cation
1 1 1 0 0 reg
mod 1 0 0 mem
1 1 1 0 0 reg
mod 1 0 0 mem
1 1 1 0 1 reg
mod 1 0 1 mem
1 1 1 0 1 reg
mod 1 0 1 mem
1 1 reg reg
mod reg mem
1 1 reg reg
mod reg mem
U
U
U
U
U
U
U
U
U
U
U
U
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
Note
The 2nd operand is omissible. If omitted, the 1st operand is assumed.