參數(shù)資料
型號(hào): UPD703100AF1-33-FA1
廠商: NEC Corp.
英文描述: V850E/MS1TM 32/16-BIT SINGLE-CHIP MICROCONTROLLERS
中文描述: V850E/MS1TM 32/16單晶片微控制器
文件頁數(shù): 64/132頁
文件大?。?/td> 1174K
代理商: UPD703100AF1-33-FA1
Preliminary Data Sheet U14168EJ2V0DS00
64
μ
PD703100A-33, 703100A-40, 703101A-33, 703102A-33
(5/7)
Execution
Clock
Flags
Mnemonic
Operand
Opcode
Operation
i
r
l
CY
OV
S
Z
SAT
SATADD
reg1,reg2
rr r r r 0 0 0 1 1 0 R R R RR
GR[reg2]
saturated(GR[reg2]+GR[reg1])
1
1
1
×
×
×
×
×
imm5,reg2
rr r r r 0 1 0 0 0 1 i i i ii
GR[reg2]
saturated(GR[reg2]+sign-
extend(imm5)
1
1
1
×
×
×
×
×
SATSUB
reg1,reg2
rr r r r 0 0 0 1 0 1 R R R RR
GR[reg2]
saturated(GR[reg2]
GR[reg1])
1
1
1
×
×
×
×
×
rr r r r 1 1 0 0 1 1 R R R RR
SATSUBI
imm16,reg1,reg2
ii i i i i i i i i i i i i ii
GR[reg2]
saturated(GR[reg1]
sign-
extend(imm16)
1
1
1
×
×
×
×
×
SATSUBR
reg1,reg2
rr r r r 0 0 0 1 0 0 R R R RR
GR[reg2]
saturated(GR[reg1]
GR[reg2])
1
1
1
×
×
×
×
×
rr r r r 1 1 1 1 1 1 0 c c cc
SETF
cccc,reg2
00 0 0 0 0 0 0 0 0 0 0 0 0 00
If conditions are satisfied
then GR[reg2]
00000001H
else GR[reg2]
00000000H
1
1
1
00 b b b 1 1 1 1 1 0 R R R RR
bit#3,disp16[reg1]
dd d d d d d d d d d d d d dd
adr
GR[reg1]+sign-extend(disp16)
Z flag
Not(Load-memory-bit(adr,bit#3))
Store-memory-bit(adr,bit#3,1)
3
Note 3
3
Note 3
3
Note 3
×
rr r r r 1 1 1 1 1 1 R R R RR
SET1
reg2,[reg1]
00 0 0 0 0 0 0 1 1 1 0 0 0 00
adr
GR[reg1]
Z flag
Not(Load-memory-bit(adr,reg2))
Store-memory-bit(adr,reg2,1)
3
Note 3
3
Note 3
3
Note 3
×
rr r r r 1 1 1 1 1 1 R R R RR
SHL
reg1,reg2
0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0
GR[reg2]
GR[reg2] logically shift left by
GR[reg1]
1
1
1
×
0
×
×
imm5,reg2
rr r r r 0 1 0 1 1 0 i i i ii
GR[reg2]
GR[reg2] logically shift left by
zero-extend(imm5)
1
1
1
×
0
×
×
rr r r r 1 1 1 1 1 1 R R R RR
SHR
reg1,reg2
0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
GR[reg2]
GR[reg2] logically shift right by
GR[reg1]
1
1
1
×
0
×
×
imm5,reg2
rr r r r 0 1 0 1 0 0 i i i ii
GR[reg2]
GR[reg2] logically shift right by
zero-extend(imm5)
1
1
1
×
0
×
×
SLD.B
disp7[ep],reg2
rr r r r 0 1 1 0 d d d d d dd
adr
ep+zero-extend(disp7)
GR[reg2]
sign-extend(Load-
memory(adr,Byte))
1
1
n
Note 9
SLD.BU
disp4[ep],reg2
Note 18
rr r r r 0 0 0 0 1 1 0 d d dd
adr
ep+zero-extend(disp4)
GR[reg2]
zero-extend(Load-
memory(adr,Byte))
1
1
n
Note 9
rr r r r 1 0 0 0 d d d d d dd
SLD.H
disp8[ep],reg2
Note 19
adr
ep+zero-extend(disp8)
GR[reg2]
sign-extend(Load-
memory(adr,Half-word))
1
1
n
Note 9
SLD.HU
disp5[ep],reg2
Notes 18, 20
rr r r r 0 0 0 0 1 1 1 d d dd
adr
ep+zero-extend(disp5)
GR[reg2]
zero-extend(Load-
memory(adr,Half-word))
1
1
n
Note 9
rr r r r 1 0 1 0 d d d d d d0
SLD.W
disp8[ep],reg2
Note 21
adr
ep+zero-extend(disp8)
GR[reg2]
Load-memory(adr,Word))
1
1
n
Note 9
SST.B
reg2,disp7[ep]
rr r r r 0 1 1 1 d d d d d dd
adr
ep+zero-extend(disp7)
Store-memory(adr,GR[reg2],Byte)
1
1
1
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