參數(shù)資料
型號： UPD703100A-40
廠商： NEC Corp.
英文描述： V850E/MS1TM 32/16-BIT SINGLE-CHIP MICROCONTROLLERS
中文描述： V850E/MS1TM 32/16單晶片微控制器
文件頁數(shù)： 98/132頁
文件大?。?/td> 1174K
代理商： UPD703100A-40
Preliminary Data Sheet U14168EJ2V0DS00
98
μ
PD703100A-33, 703100A-40, 703101A-33, 703102A-33
(c) Write timing (high-speed page DRAM access, normal access: off-page) (1/2)
Parameter
Symbol
Condition
MIN.
MAX.
Unit
WAIT setup time (to CLKOUT
↓
)
<24>
t
SWK
10
ns
WAIT hold time (from CLKOUT
↓
)
<25>
t
HKW
2
ns
Row address setup time
<56>
t
ASR
(0.5 + w
RP
) T – 10
ns
Row address hold time
<57>
t
RAH
(0.5 + w
RH
) T – 10
ns
Column address setup time
<58>
t
ASC
0.5T – 10
ns
Column address hold time
<59>
t
CAH
(1.5 + w
DA
+ w) T – 10
ns
Read/write cycle time
<60>
t
RC
(3 + w
RP
+ w
RH
+ w
DA
+ w)
T – 10
ns
RAS precharge time
<61>
t
RP
(0.5 + w
RP
) T – 5
ns
RAS pulse time
<62>
t
RAS
(2.5 + w
RH
+ w
DA
+ w)
T – 10
ns
RAS hold time
<63>
t
RSH
(1.5 + w
DA
+ w) T – 10
ns
Column address read time (from RAS
↑
)
<64>
t
RAL
(2 + w
DA
+ w) T – 10
ns
CAS pulse width
<65>
t
CAS
(1 + w
DA
+ w) T – 10
ns
CAS-RAS precharge time
<66>
t
CRP
(1 + w
RH
) T – 10
ns
CAS hold time
<67>
t
CSH
(2 + w
RH
+ w
DA
+ w)
T – 10
ns
CAS precharge time
<71>
t
CPN
(2 + w
RP
+ w
RH
) T – 5
ns
RAS column address delay time
<76>
t
RAD
(0.5 + w
RH
) T – 10
ns
RAS-CAS delay time
<77>
t
RCD
(1 + w
RH
) T – 10
ns
WE setup time (to CAS
↓
)
<84>
t
WCS
(1 + w
RP
+ w
RH
)
T – 10
ns
WE hold time (from CAS
↓
)
<85>
t
WCH
(1 + w
DA
+ w) T – 10
ns
Data setup time (to CAS
↓
)
<86>
t
DS
(1.5 + w
RP
+ w
RH
)
T –
10
ns
Data hold time (from CAS
↓
)
<87>
t
DH
(1.5 + w
DA
+ w) T – 10
ns
Remarks 1.
T = t
CYK
2.
w: the number of waits due to WAIT.
3.
w
RP
: the number of waits due to the RPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
4.
w
RH
: the number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
5.
w
DA
: the number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
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