參數(shù)資料
型號： UPD703100A-40
廠商： NEC Corp.
英文描述： V850E/MS1TM 32/16-BIT SINGLE-CHIP MICROCONTROLLERS
中文描述： V850E/MS1TM 32/16單晶片微控制器
文件頁數(shù)： 80/132頁
文件大小： 1174K
代理商： UPD703100A-40
Preliminary Data Sheet U14168EJ2V0DS00
80
μ
PD703100A-33, 703100A-40, 703101A-33, 703102A-33
(4) SRAM, external ROM, external I/O access timing
(a) Access timing (SRAM, external ROM, external I/O) (1/2)
Parameter
Symbol
Condition
MIN.
MAX.
Unit
Address, CSn output delay time (from
CLKOUT
↓
)
<16>
t
DKA
2
10
ns
Address, CSn output hold time (from
CLKOUT
↓
)
<17>
t
HKA
2
10
ns
RD, IORD
↓
delay time
(from CLKOUT
↑
)
<18>
t
DKRDL
2
14
ns
RD, IORD
↑
delay time
(from CLKOUT
↑
)
<19>
t
HKRDH
2
14
ns
UWR, LWR, IOWR
↓
delay time (from
CLKOUT
↑
)
<20>
t
DKWRL
2
10
ns
UWR, LWR, IOWR
↑
delay time (from
CLKOUT
↑
)
<21>
t
HKWRH
2
10
ns
BCYST
↓
delay time (from CLKOUT
↓
)
<22>
t
DKBSL
2
10
ns
BCYST
↑
delay time (from CLKOUT
↓
)
<23>
t
HKBSH
2
10
ns
WAIT setup time (to CLKOUT
↓
)
<24>
t
SWK
10
ns
WAIT hold time (from CLKOUT
↓
)
<25>
t
HKW
2
ns
Data input setup time
(to CLKOUT
↑
)
<26>
t
SKID
10
ns
Data input hold time
(from CLKOUT
↑
)
<27>
t
HKID
2
ns
Data output delay time
(from CLKOUT
↓
)
<28>
t
DKOD
2
10
ns
Data output hold time
(from CLKOUT
↓
)
<29>
t
HKOD
2
10
ns
Remarks 1.
Maintain at least one of the data input hold times t
HKID
and t
HRDID
.
2.
n = 0 to 7
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