參數(shù)資料
型號(hào): UPD70208HLP-12
廠商: NEC Corp.
英文描述: V40HLTM, V50HLTM 16/8, 16-BIT MICROPROCESSOR
中文描述: V40HLTM,V50HLTM 16 / 8,16位微處理器
文件頁數(shù): 73/110頁
文件大?。?/td> 625K
代理商: UPD70208HLP-12
73
μ
PD70208H, 70216H
Data Sheet U13225EJ4V0DS00
MIN.
MAX.
TOUT1
↓ →
TxD delay time
TCTL2 setup time (vs. CLKOUT
)
TCTL2 setup time (vs. TCLK
)
TCTL2 hold time (vs. CLKOUT
)
TCTL2 hold time (vs. TCLK
)
TCTL2 high-level width
TCTL2 low-level width
TOUT output delay time (vs. CLKOUT
)
TOUT output delay time (vs. TCLK
)
TOUT output delay time (vs. TCTL2
)
TCLK rise time
TCLK fall time
TCLK high-level width
TCLK low-level width
TCLK cycle
Access interval
Note 1
REFRQ
delay time (vs. MRD
)
Note 2
RESET pulse width
Note 3
(2)
μ
PD70208H, 70216H-20 (T
A
= –40 to +85
°
C, V
DD
= 5 V
±
5%) (3/3)
Output Pin Load Capacitance: C
L
= 100 pF
μ
PD70208H-20
μ
PD70216H-20
Unit
Parameter
Symbol
Notes 1.
This rating is to guarantee the read/write recovery time for the I/O device.
2.
This rating is to guarantee that REFRQ
is always behind MRD
, and guaranteed only when the EREF
bit of the STCL register is 0.
3.
When using internal clock generator by connecting a resonator to the X1 and X2 pins, the oscillation
stabilization time must be added at power-ON. Because the oscillation stabilization time varies depending
on the characteristics of the resonator and oscillator used, evaluate the oscillation stabilization time with the
resonator and oscillator actually used.
t
DTX
200
ns
t
SGK
40
ns
t
SGTK
40
ns
t
HKG
80
ns
t
HTKG
40
ns
t
GGH
40
ns
t
GGL
40
ns
t
DKTO
150
ns
t
DTKTO
100
ns
t
DGTO
90
ns
t
TKR
25
ns
t
TKF
25
ns
t
TKTKH
23
ns
t
TKTKL
23
ns
t
CYTK
50
DC
ns
t
AI
2t
CYK
–15
ns
t
DRQHRH
t
KKL
–10
ns
t
WRESL
4t
CYK
ns
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
UPD70208HLP16 制造商: 功能描述: 制造商:undefined 功能描述:
UPD70208HLP-16 制造商:NEC 制造商全稱:NEC 功能描述:V40HLTM, V50HLTM 16/8, 16-BIT MICROPROCESSOR
UPD70208HLP-20 制造商:NEC 制造商全稱:NEC 功能描述:V40HLTM, V50HLTM 16/8, 16-BIT MICROPROCESSOR
UPD70208L10 制造商:NEC 功能描述:NEW
UPD70208L-10 制造商:World Products 功能描述: