參數(shù)資料
型號(hào): UPD70208HLP-12
廠商: NEC Corp.
英文描述: V40HLTM, V50HLTM 16/8, 16-BIT MICROPROCESSOR
中文描述: V40HLTM,V50HLTM 16 / 8,16位微處理器
文件頁(yè)數(shù): 50/110頁(yè)
文件大?。?/td> 625K
代理商: UPD70208HLP-12
5
μ
P
D
AC CY V
P
S
Z
Instruc-
tion
Group
Mnemonic
Operand(s)
Operation
Operation Code
Flags
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
reg, reg’
mem, reg
reg, mem
reg, imm
mem, imm
acc, imm
reg, reg’
mem, reg
reg, mem
reg, imm
mem, imm
acc, imm
reg, reg’
mem, reg
reg, mem
reg, imm
mem, imm
acc, imm
reg, reg’
mem, reg
reg, mem
reg, imm
mem, imm
acc, imm
1 0 0 0 0 1 0 W
1 0 0 0 0 1 0 W
1 1 1 1 0 1 1 W
1 1 1 1 0 1 1 W
1 0 1 0 1 0 0 W
0 0 1 0 0 0 1 W
0 0 1 0 0 0 0 W
0 0 1 0 0 0 1 W
1 0 0 0 0 0 0 W
1 0 0 0 0 0 0 W
0 0 1 0 0 1 0 W
0 0 0 0 1 0 1 W
0 0 0 0 1 0 0 W
0 0 0 0 1 0 1 W
1 0 0 0 0 0 0 W
1 0 0 0 0 0 0 W
0 0 0 0 1 1 0 W
0 0 1 1 0 0 1 W
0 0 1 1 0 0 0 W
0 0 1 1 0 0 1 W
1 0 0 0 0 0 0 W
1 0 0 0 0 0 0 W
0 0 1 1 0 1 0 W
1 1
reg’ reg
mod reg mem
1 1 0 0 0 reg
mod
0 0 0 mem
1 1
reg
reg’
mod reg
mem
mod reg
mem
1 1 1 0 0
reg
mod
1 0 0
mem
1 1
reg
reg’
mod reg
mem
mod reg
mem
1 1 0 0 1
reg
mod
0 0 1
mem
1 1
reg
reg’
mod reg
mem
mod reg
mem
1 1 1 1 0
reg
mod
1 1 0
mem
2
2-4
3-4
3-6
2-3
2
2-4
2-4
3-4
3-6
2-3
2
2-4
2-4
3-4
3-6
2-3
2
2-4
2-4
3-4
3-6
2-3
U
0
0
×
×
×
U
0
0
×
×
×
U
0
0
×
×
×
U
0
0
×
×
×
U
0
0
×
×
×
U
0
0
×
×
×
U
0
0
×
×
×
U
0
0
×
×
×
U
0
0
×
×
×
U
0
0
×
×
×
U
0
0
×
×
×
U
0
0
×
×
×
U
0
0
×
×
×
U
0
0
×
×
×
U
0
0
×
×
×
U
0
0
×
×
×
U
0
0
×
×
×
U
0
0
×
×
×
U
0
0
×
×
×
U
0
0
×
×
×
U
0
0
×
×
×
U
0
0
×
×
×
U
0
0
×
×
×
2
9/13
4
10/14
4
2
13/21
10/14
4
15/23
4
2
13/21
10/14
4
15/23
4
2
13/21
10/14
4
15/23
4
TEST
AND
OR
XOR
L
reg reg’
(mem) reg
reg imm
(mem) imm
If W = 0: AL imm8
If W = 1: AW imm16
reg
reg reg’
(mem)
(mem) reg
reg
reg (mem)
reg
reg imm
(mem)
(mem) imm
If W = 0: AL
AL imm8
If W = 1: AW
AW imm16
reg
reg
reg’
(mem)
(mem)
reg
reg
reg
(mem)
reg
reg
imm
(mem)
(mem)
imm
If W = 0: AL
AL
imm8
If W = 1: AW
AW
imm16
reg
reg
reg’
(mem)
(mem)
reg
reg
reg
(mem)
reg
reg
imm
(mem)
(mem)
imm
If W = 0: AL
AL
imm8
If W = 1: AW
AW
imm16
Bytes
Clock Cycles
V40HL V50HL
2
9/13
4
10/14
4
2
13/21
10/14
4
15/23
4
2
13/21
10/14
4
15/23
4
2
13/21
10/14
4
15/23
4
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參數(shù)描述
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