70
μ
PD70208H, 70216H
Data Sheet U13225EJ4V0DS00
(1)
μ
PD70208H, 70216H-10/12/16 (T
A
= –40 to +85
°
C, V
DD
= 5 V
±
10%) (3/3)
t
HRX
500
500
500
ns
t
DKSR
100
100
100
ns
t
DTX
200
200
200
ns
t
SGK
40
40
40
ns
t
SGTK
40
40
40
ns
t
HKG
80
80
80
ns
t
HTKG
40
40
40
ns
t
GGH
40
40
40
ns
t
GGL
40
40
40
ns
t
DKTO
150
150
150
ns
t
DTKTO
100
100
100
ns
t
DGTO
90
90
90
ns
t
TKR
25
25
25
ns
t
TKF
25
25
25
ns
t
TKTKH
45
40
30
ns
t
TKTKL
45
40
30
ns
t
CYTK
100
DC
80
DC
62.5
DC
ns
t
AI
2t
CYK
–40
2t
CYK
–25
2t
CYK
–20
ns
t
DRQHRH
t
KKL
–30
t
KKL
–15
t
KKL
–10
ns
t
WRESL
4t
CYK
4t
CYK
4t
CYK
ns
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
R
X
D hold time (vs. SCU internal clock
↓
)
CLKOUT
↓ →
SRDY delay time
TOUT1
↓ →
T
X
D delay time
TCTL2 setup time (vs. CLKOUT
↓
)
TCTL2 setup time (vs. TCLK
↑
)
TCTL2 hold time (vs. CLKOUT
↓
)
TCTL2 hold time (vs. TCLK
↑
)
TCTL2 high-level width
TCTL2 low-level width
TOUT output delay time (vs. CLKOUT
↓
)
TOUT output delay time (vs. TCLK
↓
)
TOUT output delay time (vs. TCTL2
↓
)
TCLK rise time
TCLK fall time
TCLK high-level width
TCLK low-level width
TCLK cycle
Access interval
Note 1
REFRQ
↑
delay time (vs. MRD
↑
)
Note 2
RESET pulse width
Note 3
Unit
Symbol
Parameter
μ
PD70208H-10
μ
PD70216H-10
μ
PD70208H-16
μ
PD70216H-16
μ
PD70208H-12
μ
PD70216H-12
Output Pin Load Capacitance: C
L
= 100 pF
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Notes 1.
Specification to guarantee read/write recovery time for I/O device.
2.
Specification to guarantee that REFRQ
↑
is always later than MRD
↑
.
Only guaranteed when the EREF bit of the SCTL register is 0.
3.
When using internal clock generator by connecting a resonator to the X1 and X2 pins, the oscillation
stabilization time must be added at power-ON. Because the oscillation stabilization time varies depending
on the characteristics of the resonator and oscillator used, evaluate the oscillation stabilization time with the
resonator and oscillator actually used.