參數(shù)資料
型號(hào): UPD65966
英文描述: CMOS Gate Array.Embedded Array Ver.2.0 for Package | Design Manual[05/2003]
中文描述: CMOS門陣列Array.Embedded的包版本2.0 |設(shè)計(jì)手冊(cè)[05/2003]
文件頁數(shù): 42/64頁
文件大?。?/td> 399K
代理商: UPD65966
42
μ
PD64A, 65
Data Sheet U14380EJ2V0DS00
9.7 Branch Instructions
The program memory consists of pages in steps of 1K (000H to 3FFH). However, as the assembler automatically
performs page optimization, it is unnecessary to designate pages. The pages allowed for each product are as
follows.
μ
PD64A (ROM: 1K steps)
μ
PD65 (ROM: 2K steps)
μ
PD6P5 (PROM: 2K steps) : pages 0, 1
: page 0
: pages 0, 1
JMP addr
<1> Instruction code
: page 0
0 1 0 0 0 1 0 0 0 1
; page 1
0 1 0 0 1 1 0 0 0 1
a
9
a
7
a
6
a
5
a
4
a
8
a
3
a
2
a
1
a
0
: 1
: PC
addr
<2> Cycle count
<3> Function
The 10 bits (PC
9-0
) of the program counter are replaced directly by the specified address addr (a
9
to
a
0
).
JC addr
<1> Instruction code
: page 0
0 1 1 0 0 1 0 0 0 1
; page 1
0 1 0 1 0 1 0 0 0 1
a
9
a
7
a
6
a
5
a
4
a
8
a
3
a
2
a
1
a
0
: 1
: if
CY = 1
else
PC
PC + 2
<2> Cycle count
<3> Function
PC
addr
If the carry flag CY is set (to 1), a jump is made to the address specified with addr (a
9
to a
0
).
JNC addr
<1> Instruction code
: page 0
0 1 1 0 1 1 0 0 0 1
; page 1
0 1 0 1 1 1 0 0 0 1
a
9
a
7
a
6
a
5
a
4
a
8
a
3
a
2
a
1
a
0
: 1
: if
CY = 0
else
PC
PC + 2
<2> Cycle count
<3> Function
PC
addr
If the carry flag CY is cleared (to 0), a jump is made to the address specified with addr (a9 to a0).
JF addr
<1> Instruction code
: page 0
0 1 1 1 0 1 0 0 0 1
; page 1
1 0 0 0 0 1 0 0 0 1
a
9
a
7
a
6
a
5
a
4
a
8
a
3
a
2
a
1
a
0
: 1
: if
F = 1
else
PC
PC + 2
<2> Cycle count
<3> Function
PC
addr
If the status flag F is set (to 1), a jump is made to the address specified with addr (a
9
to a
0
).
JNF addr
<1> Instruction code
: page 0
0 1 1 1 1 1 0 0 0 1
; page 1
1 0 0 0 1 1 0 0 0 1
a
9
a
7
a
6
a
5
a
4
a
8
a
3
a
2
a
1
a
0
: 1
: if
F = 0
else
PC
PC + 2
<2> Cycle count
<3> Function
PC
addr
If the status flag F is cleared (to 0), a jump is made to the address specified with addr (a
9
to a
0
).
相關(guān)PDF資料
PDF描述
UPD65968 CMOS-9HD Family.EA-9HD Family Block Library Ver.6.0 | Block Library[12/2000]
UPD65969 CMOS Gate Array.Embedded Array Ver.2.0 for Package | Design Manual[05/2003]
UPD65970 CMOS-9HD Family.EA-9HD Family Block Library Ver.6.0 | Block Library[12/2000]
UPD65971 CMOS-9HD Family Ver.6.0 Design Manual | Design Manual[07/2001]
UPD65977S1-XXX-B6 FPGA
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
UPD65968 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CMOS-9HD Family.EA-9HD Family Block Library Ver.6.0 | Block Library[12/2000]
UPD65969 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CMOS Gate Array.Embedded Array Ver.2.0 for Package | Design Manual[05/2003]
UPD65970 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CMOS-9HD Family.EA-9HD Family Block Library Ver.6.0 | Block Library[12/2000]
UPD65971 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CMOS-9HD Family Ver.6.0 Design Manual | Design Manual[07/2001]
UPD65977S1-XXX-B6 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA