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參數(shù)資料
| 型號(hào)： | UPD65565 |
| 英文描述： | ANACONDA LT TRANSCEIVER |
| 中文描述： | CMOS門陣列Array.Embedded的包版本2.0 |設(shè)計(jì)手冊(cè)[05/2003] |
| 文件頁數(shù)： | 29/64頁 |
| 文件大小： | 399K |
| 代理商： | UPD65565 |
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29
μ
PD64A, 65
Data Sheet U14380EJ2V0DS00
8. SYSTEM CLOCK OSCILLATOR
The system clock oscillator consists of oscillators for ceramic resonators (f
X
= 2.4 to 8 MHz).
Figure 8-1. System Clock
The system clock oscillator stops its oscillation when reset or in STOP mode.
Caution When using the system clock oscillator, wire area indicated by the dotted-line in the diagram
as follows to reduce the effects of the wiring capacitance, etc.
Make the wiring as short as possible.
Do not allow the wiring to intersect other signal lines. Do not wire close to lines through
which large fluctuating currents flow.
Make sure that the point where the oscillator capacitor is installed is always at the same
electric potential as the ground. Never earth with a ground pattern through which large
currents flow.
Do not extract signals from the oscillator.
PD64A, 65
μ
X
OUT
X
IN
GND
Ceramic resonator
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