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參數(shù)資料
| 型號： | UPD65565 |
| 英文描述： | ANACONDA LT TRANSCEIVER |
| 中文描述： | CMOS門陣列Array.Embedded的包版本2.0 |設(shè)計手冊[05/2003] |
| 文件頁數(shù)： | 21/64頁 |
| 文件大?。?/td> | 399K |
| 代理商： | UPD65565 |
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21
μ
PD64A, 65
Data Sheet U14380EJ2V0DS00
4.3 Carrier Output
The carrier for remote-controlled transmission can be output from the REM pin by clearing (to 0) bit 2 of the control
register 0.
As shown in Figure 4-3, in the case where the timer stops when the carrier is at a high level, the carrier continues
to be output until its next fall and then stops due to the function of the carrier synchronous circuit. When the timer
starts operation, however, the high-level width of the first carrier may become shorter than the specified width.
Figure 4-3. Timer Output (when carrier is output)
Timer value: (Set value+1)
×
64/f
X
(or 128/f
X
)
LED
REM (at low-level start)
REM (at high-level start)
Note 1
Note 2
Notes 1.
Error when the REM output ends: Lead by “the carrier’s low-level width” to lag by “the carrier’s high-
level width”
2.
Error of the carrier’s high-level width: 0 to “the carrier’s high-level width”
4.4 Software Control of Timer Output
The timer output can be controlled by software. As shown in Figure 4-4, the pulse with a minimum width of 1-
instruction cycle (64/f
X
) can be output.
Figure 4-4. Pulse Output of 1-Instruction Cycle Width
MOV T, #0000000000B; low-level output from the REM pin
MOV T, #1000000000B; high-level output from the REM pin
MOV T, #0000000000B; low-level output from the REM pin
…
64/f
X
LED
REM
…
…
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