參數(shù)資料
型號(hào)： UPD44321362GF-A50
廠商： NEC Corp.
英文描述： 32M-BIT ZEROSB SRAM PIPELINED OPERATIO
中文描述： 32兆位ZEROSB SRAM的流水線OPERATIO
文件頁(yè)數(shù)： 9/24頁(yè)
文件大小： 299K
代理商： UPD44321362GF-A50
9
Data Sheet M16024EJ5V0DS
μ
PD44321182, 44321362
State Diagram
DESELECT
BEGIN
READ
BURST
READ
BEGIN
WRITE
BURST
WRITE
WRITE
READ
READ
DS
DS
WRITE
READ
BURST
BURST
WRITE
READ
WRITE
READ
BURST
WRITE
BURST
DS
BURST
DS
DS
Command
Operation
DS
Deselect
Read
New Read
Write
New Write
Burst
Burst Read, Burst Write or Continue Deselect
Remarks 1.
States change on the rising edge of the clock.
2.
A Stall or Ignore Clock Edge cycle is not shown in the above diagram. This is because /CKE HIGH
only blocks the clock (CLK) input and does not change the state of the device.
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UPD44324362BF5-E40-FQ1-A 制造商:Renesas Electronics Corporation 功能描述:36MB, DDRII SRAM - Trays 制造商:Renesas Electronics Corporation 功能描述:IC SRAM DDRII 36MBIT 165BGA
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