參數(shù)資料
型號(hào)： UPD44321362GF-A50
廠商： NEC Corp.
英文描述： 32M-BIT ZEROSB SRAM PIPELINED OPERATIO
中文描述： 32兆位ZEROSB SRAM的流水線OPERATIO
文件頁數(shù)： 4/24頁
文件大?。?/td> 299K
代理商： UPD44321362GF-A50
4
Data Sheet M16024EJ5V0DS
μ
PD44321182, 44321362
Pin Identifications
[
μ
PD44321182GF]
Symbol
Pin No.
Description
A0 to A20
37, 36, 35, 34, 33, 32, 100, 99, 82, 81, 44, Synchronous Address Input
45, 46, 47, 48, 49, 50, 83, 84, 43, 80
I/O1 to I/O16
58, 59, 62, 63, 68, 69, 72, 73, 8, 9, 12, 13, Synchronous Data In,
18, 19, 22, 23
Synchronous / Asynchronous Data Out
I/OP1, I/OP2
74, 24
Synchronous Data In (Parity),
Synchronous / Asynchronous Data Out (Parity)
ADV
85
Synchronous Address Load / Advance Input
/CE, CE2, /CE2
98, 97, 92
Synchronous Chip Enable Input
/WE
88
Synchronous Write Enable Input
/BW1, /BW2
93, 94
Synchronous Byte Write Enable Input
/G
86
Asynchronous Output Enable Input
CLK
89
Clock Input
/CKE
87
Synchronous Clock Enable Input
MODE
31
Asynchronous Burst Sequence Select Input
Have to tied to V
DD
or V
SS
during normal operation
ZZ
64
Asynchronous Power Down State Input
V
DD
14, 15, 16, 41, 65, 66, 91
Power Supply
V
SS
17, 40, 67, 90
Ground
V
DD
Q
4, 11, 20, 27, 54, 61, 70, 77
Output Buffer Power Supply
V
SS
Q
5, 10, 21, 26, 55, 60, 71, 76
Output Buffer Ground
NC
1, 2, 3, 6, 7, 25, 28, 29, 30, 38, 39, 42, 51, No Connection
52, 53, 56, 57, 75, 78, 79, 95, 96
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